AM50DL128CG70I AMD (ADVANCED MICRO DEVICES), AM50DL128CG70I Datasheet
AM50DL128CG70I
Specifications of AM50DL128CG70I
Related parts for AM50DL128CG70I
AM50DL128CG70I Summary of contents
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Am50DL128CG Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, ...
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PRELIMINARY Am50DL128CG Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Two Am29DL640G 64 Megabit ( 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit ( 16-Bit) Pseudo Static RAM with Page Mode DISTINCTIVE CHARACTERISTICS ...
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GENERAL DESCRIPTION Am29DL640G Features The Am29DL640G megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each. Word mode data appears on DQ15–DQ0. The device is designed to be programmed in-system with the standard ...
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TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . . . . . . . . ...
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Data Retention . . . . . . . . . . . . . . . . . . . . . 58 pSRAM Power on and Deep Power Down . . . . . 58 Figure 32. ...
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PRODUCT SELECTOR GUIDE Part Number Speed Standard Voltage Range: Options V = 2.7–3 Max Access Time, ns Page Access Time (pSRAM), ns CE#f Access, ns OE# Access, ns MCP BLOCK DIAGRAM RESET#1 CE#f1 WP#/ACC RESET#2 CE#f2 LB# UB# ...
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FLASH MEMORY BLOCK DIAGRAM Mux A21–A0 RY/BY# A21–A0 STATE RESET# CONTROL WE# & COMMAND CE# REGISTER BYTE# WP#/ACC DQ15–DQ0 A21–A0 Mux OE# BYTE# Bank ...
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CONNECTION DIAGRAM RY/BY CE#f1 OE CE#1fps ...
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PIN DESCRIPTION A21– Address Inputs (Common) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f1 = Chip Enable 1 (Flash 1) CE#f2 = Chip Enable 2 (Flash 2) CE1#ps = Chip Enable 1 (pSRAM) CE2ps = Chip Enable 2 (pSRAM) ...
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... TAPE AND REEL inches inches TEMPERATURE RANGE I = Industrial (– +85 C) SPEED OPTION See “Product Selector Guide” on page 5 FLASH PROCESS TECHNOLOGY G = 0.17 µm PSEUDO SRAM DEVICE DENSITY Mbits Order Number Am50DL128CG70I Am50DL128CG85I Am50DL128CG Valid Combinations Package Marking T, S M500000008 T, S M500000009 9 ...
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MCP DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a ...
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Table 1. Device Bus Operations—Flash Word Mode CE#f CE#f Operation Active Inactive CE1#ps CE2ps OE# WE# (Notes 1, 2) (Note 3) (Note 8) Read from L H Active Flash (Note 9) (Note 8) Write to Active L H Flash (Note ...
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FLASH DEVICE BUS OPERATIONS Word Configuration The device is in word configuration, DQ15–DQ0 are active and controlled by CE#f and OE#. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE#f and ...
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CE#f and RESET# are held within V ± 0.3 V, the device will be in the standby CC mode, but the standby current will ...
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Table 2. Am29DL640G Sector Architecture Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 Bank 1 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 ...
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Table 2. Am29DL640G Sector Architecture (Continued) Bank Sector SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 Bank 2 SA47 SA48 SA49 SA50 SA51 SA52 ...
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Table 2. Am29DL640G Sector Architecture (Continued) Bank Sector SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 Bank 3 SA95 SA96 SA97 SA98 SA99 SA100 ...
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Table 2. Am29DL640G Sector Architecture (Continued) Bank Sector SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 Bank 4 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 Note: The address range is A21:A0. Bank ...
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Sector/Sector Block Protection and Unprotection (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see ...
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If the system asserts V on the WP#/ACC pin, the de- IH vice reverts to whether sectors 0, 1, 140, and 141 were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors de- ...
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START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...
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SecSi™ (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 256 bytes in length, and uses a ...
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START If data = 00h, RESET# = SecSi Sector unprotected. If data = 01h, SecSi Sector is Wait 1 s protected. Write 60h to any address Remove V from RESET# Write 40h to ...
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Addresses (Word Mode) Data 10h 0051h 11h 0052h 12h 0059h 13h 0002h 14h 0000h 15h 0040h 16h 0000h 17h 0000h 18h 0000h 19h 0000h 1Ah 0000h Addresses (Word Mode) Data 1Bh 0027h 1Ch 0036h 1Dh 0000h 1Eh 0000h 1Fh 0004h ...
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Addresses (Word Mode) Data 27h 0017h 28h 0002h 29h 0000h 2Ah 0000h 2Bh 0000h 2Ch 0003h 2Dh 0007h 2Eh 0000h 2Fh 0020h 30h 0000h 31h 007Dh 32h 0000h 33h 0000h 34h 0001h 35h 0007h 36h 0000h 37h 0020h 38h 0000h ...
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Table 10. Primary Vendor-Specific Extended Query Addresses (Word Mode) Data 40h 0050h 41h 0052h 42h 0049h 43h 0031h 44h 0033h 45h 0004h 46h 0002h 47h 0001h 48h 0001h 49h 0004h 0077h 4Ah 4Bh 0000h 4Ch 0000h 4Dh 0085h 4Eh 0095h ...
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FLASH COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 11 defines the valid register command sequences. Writing incorrect address and data val- ues or writing them in the ...
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Sector command sequence. The device continues to access the SecSi Sector region until the system is- sues the four-cycle Exit SecSi Sector command se- quence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector ...
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Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed Note: See Table 11 for program command sequence. Figure 4. Program Operation Chip Erase Command Sequence Chip erase ...
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DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Flash Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only ...
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Table 11. Am29DL640G Command Definitions Command Sequence (Note 1) Addr Read (Note 6) 1 Reset (Note 7) 1 XXX Manufacturer ID Word 4 Device ID (Note 9) Word 6 SecSi Sector Factory Word 4 Protect (Note 10) Sector/Sector Block Protect ...
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FLASH WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 12 and the following subsections describe the function of these bits. DQ7 and DQ6 ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...
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DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . – +125 C Ambient Temperature with Power Applied . . . . . . . . ...
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FLASH DC CHARACTERISTICS CMOS Compatible Parameter Parameter Description Symbol I Input Load Current LI I RESET# Input Load Current LIT I Output Leakage Current LO I Reset Leakage Current LR I ACC Input Leakage Current LIA Flash V Active Read ...
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DC & OPERATING CHARACTERISTICS Parameter Parameter Description Symbol I Input Leakage Current LI I Output Leakage Current LO Operating Power Supply I CC Current I s Operating Current CC1 Page Access Operating I s CC2 Current V Output Low ...
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FLASH DC CHARACTERISTICS Zero-Power Flash 500 Note: Addresses are switching at 1 MHz Figure 10. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...
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TEST CONDITIONS Device Under Test C 6 Note: Diodes are IN3064 or equivalent Figure 12. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V 1.5 V Input 0.0 V Figure 13. Input Waveforms ...
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AC CHARACTERISTICS CE#s Timing Parameter JEDEC Std Description — t CE#s Recover Time CCR CE#f CE1#s CE2s Figure 14. Timing Diagram for Alternating — t CCR t ...
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FLASH AC CHARACTERISTICS Read-Only Operations Parameter JEDEC Std. Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to ...
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FLASH AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read Mode (See Note) t RESET# Pulse Width ...
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FLASH AC CHARACTERISTICS Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS t Address Setup Time to OE# low during toggle bit polling ASO t ...
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FLASH AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE#f t GHWL OE# WE Data RY/BY VCS Notes program address program data Illustration ...
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FLASH AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE#f t GHWL OE WE Data RY/BY# t VCS Notes: 1. SADD = sector address (for Sector Erase), ...
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FLASH AC CHARACTERISTICS t WC Valid PA Addresses t AH CE#f OE WE# t WPH t DS Valid Data In WE# Controlled Write Cycle Note: CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The ...
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FLASH AC CHARACTERISTICS Addresses CE#f t OEH WE# OE Valid Data DQ6/DQ2 RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array ...
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FLASH AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR Rise and Fall Time (See Note) VHH HH RESET# Setup Time for Temporary Sector t RSP Unprotect RESET# ...
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FLASH AC CHARACTERISTICS RESET# SADD, A6, A1, A0 Sector/Sector Block Protect or Unprotect Data 60h 1 µs CE#f WE# OE# * For sector protect For sector unprotect, ...
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FLASH AC CHARACTERISTICS Alternate CE#f Controlled Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time ELAX Data ...
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FLASH AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation ...
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AC CHARACTERISTICS Read Cycle Parameter Description Symbol t Read Cycle Time RC t Address Access Time ACC t Chip Enable Access Time CO t Output Enable Access Time OE t Data Byte Control Access Time BA t Chip Enable ...
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AC CHARACTERISTICS Addresses Addresses A20 to A3 CE#1 CE2 OE# WE# LB#, UB# D OUT DQ15 to DQ0 t COE t ACC Notes and t are defined as the time ...
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AC CHARACTERISTICS Write Cycle Parameter Description Symbol t Write Cycle Time WC t Write Pulse Time WP t Chip Enable to End of Write CW t Data Byte Control to End of Write BW t Address Setup Time AS ...
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AC CHARACTERISTICS Addresses A20 WE# CE CE2 LB#, UB# D High-Z OUT DQ15 to DQ0 D IN (Note 1) DQ15 to DQ0 Notes the device is using the I/Os to output ...
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AC CHARACTERISTICS Addresses A20 WE# CE CE2 UB#, LB# D High-Z OUT DQ15 to DQ0 D IN DQ15 to DQ0 Notes the device is using the I/Os to output data, input ...
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FLASH ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Program Time Accelerated Byte/Word Program Time Word Program Time Byte Mode Chip Program Time (Note 3) Word Mode Notes: 1. Typical program and erase times assume the ...
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DATA RETENTION Parameter Parameter Description Symbol V V for Data Retention Data Retention Current DR t CE2 Setup Time CS t CE2 Hold Time CH t CE2 Pulse Width DPD t CE2 Hold from CE#1 CHC ...
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ADDRESS SKEW CE#1 WE# Address Note: If multiple invalid address cycles shorter than t cycle over t is required during that period. RC min CE#1 WE# Address Note: If multiple invalid address cycles shorter than t cycle over t ...
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PHYSICAL DIMENSIONS FTA088—88-Ball Fine-Pitch Grid Array 11 0.15 C (2X) INDEX MARK PIN A1 CORNER 10 TOP VIEW SIDE VIEW 6 b 88X 0. 0. PACKAGE FTA ...
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REVISION SUMMARY Revision A (September 30, 2002) Initial release. Revision A+1 (October 15, 2002) Global Replaced the 73-Ball FBGA package with the 88-Ball FBGA. Pin Description Changed references from sRAM to psRAM Added RY/BY#2 and RESET#2 Revision A+2 (November 7, ...
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Trademarks Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this ...