AM50DL128CG70I AMD (ADVANCED MICRO DEVICES), AM50DL128CG70I Datasheet - Page 55

• Manufacturer Part Number: AM50DL128CG70I
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM50DL128CG70I

• Lead Free Status / RoHS Status: Supplier Unconfirmed

pSRAM AC CHARACTERISTICS
Write Cycle
Notes:
1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.
2. If OE# is high during the write cycle, the outputs will remain at high impedance.
3. If CE#1s, LB# or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance.
4. If CE#1s, LB# or UB# goes high at the same time or before WE# goes high, the outputs will remain at high impedance.
54
DQ15 to DQO
DQ15 to DQ0
Parameter
Symbol
Addresses
A20 to A0
LB#, UB#
t
t
t
t
t
ODW
t
t
OEW
t
t
t
t
WC
CW
WR
WP
BW
AS
DS
DH
CH
CE#1
D
WE#
CE2
OUT
D
IN
Description
Write Cycle Time
Write Pulse Time
Chip Enable to End of Write
Data Byte Control to End of Write
Address Setup Time
Write Recovery Time
WE# Low to Write to Output High-Z
WE# High to Write to Output Active
Data Set-up Time
Data Hold from Write Time
CE2 Hold Time
(Note 1)
(Note 3)
t
CH
Figure 29. Pseudo SRAM Write Cycle—WE# Control
t
AS
P R E L I M I N A R Y
t
ODW
Am50DL128CG
t
CW
t
BW
t
WC
t
WP
Max
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
High-Z
Valid Data In
t
DS
70
70
50
60
60
t
OEW
t
DH
Speed
t
WR
300
20
30
0
0
0
0
85
85
60
70
70
(Note 4)
November 7, 2002
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs