NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 175
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NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
Lead Free Status / RoHS Status
Compliant
- Current page: 175 of 848
- Download datasheet (7Mb)
Functional Description
5.14.11.4
5.14.11.5
5.14.11.6
5.14.11.7
Intel
®
ICH7 Family Datasheet
CPUPWRGD Signal
This signal is connected to the processor’s VRM via the VRMPWRGD signal and is
internally AND’d with the PWROK signal that comes from the system power supply.
VRMPWRGD Signal
VRMPWRGD is an input from the regulator indicating that all of the outputs from the
regulator are on and within specification. VRMPWRGD may go active before or after the
PWROK from the main power supply. ICH7 has no dependency on the order in which
these two signals go active or inactive.
BATLOW# (Battery Low) (Mobile/Ultra Mobile Only)
The BATLOW# input can inhibit waking from S3, S4, and S5 states if there is not
sufficient power. It also causes an SMI# if the system is already in an S0 state.
Controlling Leakage and Power Consumption
during Low-Power States
To control leakage in the system, various signals tri-state or go low during some low-
power states.
General principles:
Based on the above principles, the following measures are taken:
• All signals going to powered down planes (either internally or externally) must be
• Signals with pull-up resistors should not be low during low-power states. This is to
• Buses should be halted (and held) in a known state to avoid a floating input
• During S3 (STR), all signals attached to powered down planes are tri-stated or
either tri-stated or driven low.
avoid the power consumed in the pull-up resistor.
(perhaps to some other device). Floating inputs can cause extra power
consumption.
driven low.
175
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