NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 389
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NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
Lead Free Status / RoHS Status
Compliant
- Current page: 389 of 848
- Download datasheet (7Mb)
LPC Interface Bridge Registers (D31:F0)
10.2.6
Intel
®
ICH7 Family Datasheet
DMA_WRSMSK—DMA Write Single Mask Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
7:3
1:0
Bit
2
Reserved. Must be 0.
Channel Mask Select — WO.
0 = Enable DREQ for the selected channel. The channel is selected through bits [1:0].
1 = Disable DREQ for the selected channel.
DMA Channel Select — WO. These bits select the DMA Channel Mode Register to
program.
00 = Channel 0 (4)
01 = Channel 1 (5)
10 = Channel 2 (6)
11 = Channel 3 (7)
Therefore, only one channel can be masked / unmasked at a time.
Ch. #0
Ch. #4
0000 01xx
No
–
–
3 = 0Ah;
7 = D4h
Description
Attribute:
Size:
Power Well:
WO
8-bit
Core
389
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