NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 531

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.3.2.1
12.3.2.2
12.3.2.3
Intel
®
ICH7 Family Datasheet
PxCLB—Port [3:0] Command List Base Address Register
(D31:F2)
Address Offset: Port 0: ABAR + 100h
Default Value:
PxCLBU—Port [3:0] Command List Base Address Upper
32-Bits Register (D31:F2)
Address Offset: Port 0: ABAR + 104h
Default Value:
PxFB—Port [3:0] FIS Base Address Register (D31:F2)
Address Offset: Port 0: ABAR + 108h
Default Value:
31:10
31:0
31:8
9:0
7:0
Bit
Bit
Bit
Command List Base Address (CLB) — R/W. Indicates the 32-bit base for the
command list for this port. This base is used when fetching commands to execute. The
structure pointed to by this address range is 1 KB in length. This address must be 1-KB
aligned as indicated by bits 31:10 being read/write.
Note that these bits are not reset on a HBA reset.
Reserved — RO
Command List Base Address Upper (CLBU) — R/W. Indicates the upper 32-bits for
the command list base address for this port. This base is used when fetching
commands to execute.
Note that these bits are not reset on a HBA reset.
FIS Base Address (FB) — R/W. Indicates the 32-bit base for received FISes. The
structure pointed to by this address range is 256 bytes in length. This address must be
256-byte aligned, as indicated by bits 31:3 being read/write.
Note that these bits are not reset on a HBA reset.
Reserved — RO
Port 1: ABAR + 180h (ICH7R and ICH7DH Only)
Port 2: ABAR + 200h
Port 3: ABAR + 280h (ICH7R and ICH7DH Only)
Undefined
Port 1: ABAR + 184h (ICH7R and ICH7DH Only)
Port 2: ABAR + 204h
Port 3: ABAR + 284h (ICH7R and ICH7DH Only)
Undefined
Port 1: ABAR + 188h (ICH7R and ICH7DH Only)
Port 2: ABAR + 208h
Port 3: ABAR + 288h (ICH7R and ICH7DH Only)
Undefined
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
R/W, RO
32 bits
R/W
32 bits
R/W, RO
32 bits
531