NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 506
NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
Lead Free Status / RoHS Status
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12.1.26
12.1.27
f
506
PID—PCI Power Management Capability Identification
Register (SATA–D31:F2)
Address Offset: 70h
Default Value:
PC—PCI Power Management Capabilities Register
(SATA–D31:F2)
Address Offset: 72h
Default Value:
15:11
15:8
Bits
Bits
7:0
8:6
2:0
10
9
5
4
3
Next Capability (NEXT) — RO.
00h — if SCC = 01h (IDE mode).
A8h — for all other values of SCC to point to the next capability structure.
This field is changed to 00h if the SCRD bit (D31:F2;Offset 94h bit-30) is set.
Capability ID (CID) — RO. Indicates that this pointer is a PCI power management.
PME Support (PME_SUP) — RO. Indicates PME# can be generated from the D3
in the SATA host controller.
D2 Support (D2_SUP) — RO. Hardwired to 0. The D2 state is not supported
D1 Support (D1_SUP) — RO. Hardwired to 0. The D1 state is not supported
Auxiliary Current (AUX_CUR) — RO. PME# from D3COLD state is not supported,
therefore this field is 000b.
Device Specific Initialization (DSI) — RO. Hardwired to 0 to indicate that no device-
specific initialization is required.
Reserved
PME Clock (PME_CLK) — RO. Hardwired to 0 to indicate that PCI clock is not required to
generate PME#.
Version (VER) — RO. Hardwired to 010 to indicates support for Revision 1.1 of the PCI
Power Management Specification.
XX01h
4002h
–
–
71h
73h
SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
Description
Description
Attribute:
Size:
Attribute:
Size:
Intel
RO
16 bits
RO
16 bits
®
ICH7 Family Datasheet
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