NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 532

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

12.3.2.4
12.3.2.5
532
PxFBU—Port [3:0] FIS Base Address Upper 32-Bits
Register (D31:F2)
Address Offset: Port 0: ABAR + 10Ch
Default Value:
PxIS—Port [3:0] Interrupt Status Register (D31:F2)
Address Offset: Port 0: ABAR + 110h
Default Value:
31:3
2:0
Bit
Bit
31
30
29
28
27
26
25
24
23
22
FIS Base Address Upper (FBU) — R/W. Indicates the upper 32-bits for the received
FIS base for this port.
Note that these bits are not reset on a HBA reset.
Reserved
Cold Port Detect Status (CPDS) — RO. Cold presence not supported.
Task File Error Status (TFES) — R/WC. This bit is set whenever the status register is
updated by the device and the error bit (PxTFD.bit 0) is set.
Host Bus Fatal Error Status (HBFS) — R/WC. Indicates that the Intel
encountered an error that it cannot recover from due to a bad software pointer. In PCI,
such an indication would be a target or master abort.
Host Bus Data Error Status (HBDS) — R/WC. Indicates that the ICH7 encountered a
data error (uncorrectable ECC / parity) when reading from or writing to system
memory.
Interface Fatal Error Status (IFS) — R/WC. Indicates that the ICH7 encountered an
error on the SATA interface which caused the transfer to stop.
Interface Non-fatal Error Status (INFS) — R/WC. Indicates that the ICH7
encountered an error on the SATA interface but was able to continue operation.
Reserved
Overflow Status (OFS) — R/WC. Indicates that the ICH7 received more bytes from a
device than was specified in the PRD table for the command.
Incorrect Port Multiplier Status (IPMS) — R/WC. Indicates that the ICH7 received
a FIS from a device whose Port Multiplier field did not match what was expected.
NOTE: Port Multiplier not supported by ICH7.
PhyRdy Change Status (PRCS) — RO. When set to one indicates the internal PhyRdy
signal changed state. This bit reflects the state of PxSERR.DIAG.N. Unlike most of the
other bits in the register, this bit is RO and is only cleared when PxSERR.DIAG.N is
cleared.
Note that the internal PhyRdy signal also transitions when the port interface enters
partial or slumber power management states. Partial and slumber must be disabled
when Surprise Removal Notification is desired, otherwise the power management state
transitions will appear as false insertion and removal events.
Port 1: ABAR + 18Ch
Port 2: ABAR + 20Ch
Port 3: ABAR + 28Ch
Undefined
Port 1: ABAR + 190h (ICH7R and ICH7DH Only)
Port 2: ABAR + 210h
Port 3: ABAR + 290h (ICH7R and ICH7DH Only
00000000h
SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
Description
Description
Attribute:
Size:
Attribute:
Size:
Intel
R/W
32 bits
R/WC, RO
32 bits
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ICH7 Family Datasheet
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ICH7