NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 325
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NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
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Compliant
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LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.2.11
Intel
®
ICH7 Family Datasheet
GENCNTL—General Control Register
(LAN Controller—B1:D8:F0)
Offset Address: 1Ch
Default Value:
7:4
Bit
Bit
2
1
0
3
2
1
0
Reserved. These bits should be set to 0000b.
LAN Connect Software Reset
0 = Cleared by software to begin normal LAN Connect operating mode. Software must
1 = Software can set this bit to force a reset condition on the LAN Connect interface.
Reserved. This bit should be set to 0.
Deep Power-Down on Link Down Enable
0 = Disable
1 = Enable. The Intel
Reserved
ASF Enabled — RO. This bit is set to 1 when the LAN controller is in ASF mode.
TCO Request — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set to 1b when the LAN controller is busy with TCO activity.
PME Status — R/WC. This bit is a reflection of the PME Status bit in the Power
Management Control/Status Register (PMCSR).
0 = Software clears this bit by writing a 1 to it.This also clears the PME Status bit in the
1 = Set upon a wake-up event, independent of the PME Enable bit.
not attempt to access the LAN Connect interface for at least 1ms after clearing this
bit.
state (sub-3 mA) in the D2 and D3 power states while the link is down. In this
state, the LAN controller does not keep link integrity. This state is not supported for
point-to-point connection of two end stations.
PMCSR and deasserts the PME signal.
00h
®
ICH7’s internal LAN controller may enter a deep power-down
—
R/W.
Description
Description
Attribute:
Size:
—
R/W.
R/W
8 bits
325
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