NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 630
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NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
Lead Free Status / RoHS Status
Compliant
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16.1.23
630
PCS—Power Management Control and Status Register
(Audio—D30:F2)
Address Offset: 54h
Default Value:
Lockable:
14:9
7:2
1:0
Bit
15
8
PME Status (PMES) — R/WC. This bit resides in the resume well. Software clears this
bit by writing a 1 to it.
0 = PME# signal Not asserted by AC ‘97 controller.
1 = This bit is set when the AC ’97 controller would normally assert the PME# signal
Reserved — RO.
Power Management Event Enable (PMEE) — R/W.
0 = Disable.
1 = Enable. When set, and if corresponding PMES is also set, the AC '97 controller sets
Reserved—RO.
Power State (PS) — R/W. This field is used both to determine the current power state
of the AC ’97 controller and to set a new power state. The values are:
00 = D0 state
01 = not supported
10 = not supported
11 = D3
When in the D3
the I/O and memory spaces are not. Additionally, interrupts are blocked.
If software attempts to write a value of 10b or 01b in to this field, the write operation
must complete normally; however, the data is discarded and no state change occurs.
independent of the state of the PME_En bit.
the AC97_STS bit in the GPE0_STS register
HOT
0000h
No
state
–
55h
HOT
state, the AC ’97 controller’s configuration space is available, but
AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
Description
Attribute:
Size:
Power Well:
Intel
R/W, R/WC
16 bits
Resume
®
ICH7 Family Datasheet
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