876784 Intel, 876784 Datasheet - Page 335

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.3.8
Note:
.
8.3.9
Intel
®
ICH7 Family Datasheet
HEART_TIM—Heartbeat Timer Register
(ASF Controller—B1:D8:F0)
Offset Address: E9h
Default Value:
The HeartBeat Timer register implements the heartbeat timer. This defines the period
of the heartbeats packets. It contains a down counting value when enabled and the
time-out value when the counter is disabled. The timer can be configured and enabled
in a single write.
The heartbeat timer controls the heartbeat status packet frequency. The timer is free-
running and the configured time is only valid from one heartbeat to the next. When
enabled by software, the next heartbeat may occur in any amount of time less than the
configured time.
RETRAN_INT—Retransmission Interval Register
(ASF Controller—B1:D8:F0)
Offset Address: EAh
Default Value:
This register implements the retransmission timer. This is the time between packet
transmissions for multiple packets due to a SOS.
7:1
7:1
Bit
Bit
0
0
Heartbeat Timer Value (HBT_VAL) — R/W. Heartbeat timer load value in
10.7-second resolution. This field can only be written while the timer is disabled.
(10.7 sec – 23 min range). Read as load value when HBT_ENA=0. Read as
decrementing value when HBT_ENA=1. Timer resolution is 10.7 seconds. A value of
00h is invalid.
Timer Enable (HBT_ENA) — R/W.
0 = Disable
1 = Enable / Reset Counter
Retransmit Timer Value (RTM_VAL) — R/W. Retransmit timer load value 2.7 second
resolution. This field is always writable (2.7 sec – 5.7 min range). Timer is accurate to
+0 seconds, –0.336 seconds. Reads always show the load value (decrement value not
shown). A value of 00h is invalid.
Reserved
02h
02h
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W
8 bits
R/W
8 bits
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