876784 Intel, 876784 Datasheet - Page 573

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

EHCI Controller Registers (D29:F7)
13.2.2.7
13.2.2.8
13.2.2.9
Intel
®
ICH7 Family Datasheet
ASYNCLISTADDR—Current Asynchronous List Address
Register
Offset:
Default Value:
This 32-bit register contains the address of the next asynchronous queue head to be
executed. Since the ICH7 host controller operates in 64-bit mode (as indicated by a 1 in
64-bit Addressing Capability field in the HCCPARAMS register) (offset 08h, bit 0), then
the most significant 32 bits of every control data structure address comes from the
CTRLDSSEGMENT register (offset 08h). Bits [4:0] of this register cannot be modified by
system software and will always return 0’s when read. The memory structure
referenced by this physical memory pointer is assumed to be 32-byte aligned.
CONFIGFLAG—Configure Flag Register
Offset:
Default Value:
This register is in the suspend power well. It is only reset by hardware when the
suspend power is initially applied or in response to a host controller reset.
PORTSC—Port N Status and Control Register
Offset:
Attribute:
Default Value:
A host controller must implement one or more port registers. Software uses the N_Port
information from the Structural Parameters Register to determine how many ports
need to be serviced. All ports have the structure defined below. Software must not
write to unreported Port Status and Control Registers.
31:5
31:1
4:0
Bit
Bit
0
Link Pointer Low (LPL) — R/W. These bits correspond to memory address signals
[31:5], respectively. This field may only reference a Queue Head (QH).
Reserved. These bits are reserved and their value has no effect on operation.
Reserved. Read from this field will always return 0.
Configure Flag (CF) — R/W. Host software sets this bit as the last action in its process
of configuring the Host controller. This bit controls the default port-routing control logic.
Bit values and side-effects are listed below. See section 4 of the EHCI spec for
operation details.
0 = Port routing control logic default-routes each port to the classic host controllers
1 = Port routing control logic default-routes all ports to this host controller.
(default).
MEM_BASE + 38h–3Bh
00000000h
MEM_BASE + 60h–63h
00000000h
Port 0: MEM_BASE + 64h
Port 1: MEM_BASE + 68
Port 2: MEM_BASE + 6C
Port 3: MEM_BASE + 70
Port 4: MEM_BASE + 74
Port 5: MEM_BASE + 78
Port 6: MEM_BASE + 7C
Port 7: MEM_BASE + 80
R/W, R/WC, RO
00003000h
Description
Description
–
–
–
–
–
–
–
6Bh
6Fh
73h
77h
7Bh
7Fh
83h
–
67h
Attribute:
Size:
Attribute:
Size:
Size:
R/W
32 bits
R/W
32 bits
32 bits
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