876784 Intel, 876784 Datasheet - Page 739

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Intel® High Definition Audio Controller Registers (D27:F0)
19.2.13
Intel
®
ICH7 Family Datasheet
INTCTL—Interrupt Control Register
(Intel
Memory Address:HDBAR + 20h
Default Value:
29:8
7:0
Bit
31
30
Global Interrupt Enable (GIE) — R/W. Global bit to enable device interrupt
generation.
0 = Disable.
1 = Enable. The Intel
NOTE: This bit is not affected by the D3
Controller Interrupt Enable (CIE) — R/W. Enables the general interrupt for
controller functions.
0 = Disable.
1 = Enable. The controller generates an interrupt when the corresponding status bit
NOTE: This bit is not affected by the D3
Reserved
Stream Interrupt Enable (SIE) — R/W.
0 = Disable.
1 = Enable. When set to 1, the individual streams are enabled to generate an interrupt
A stream interrupt will be caused as a result of a buffer with IOC = 1in the BDL entry
being completed, or as a result of a FIFO error (underrun or overrun) occurring. Control
over the generation of each of these sources is in the associated Stream Descriptor.
The streams are numbered and the SIE bits assigned sequentially, based on their order
in the register set.
Bit 0 = input stream 1
Bit 1 = input stream 2
Bit 2 = input stream 3
Bit 3 = input stream 4
Bit 4 = output stream 1
Bit 5 = output stream 2
Bit 6 = output stream 3
Bit 7 = output stream 4
®
High Definition Audio Controller—D27:F0)
interrupt. This control is in addition to any bits in the bus specific address space,
such as the Interrupt Enable bit in the PCI configuration space.
gets set due to a Response Interrupt, a Response Buffer Overrun, and State
Change events.
when the corresponding status bits get set.
00000000h
®
High Definition Audio function is enabled to generate an
Description
HOT
HOT
Attribute:
Size:
to D0 transition.
to D0 transition.
R/W
32 bits
739