876784 Intel, 876784 Datasheet - Page 85

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

Intel
Table 3-3.
Intel
®
®
ICH7 Pin States
ICH7 Family Datasheet
EL_RSVD / GPIO26
EL_STATE[1:0] /
Signal Name
Power Plane and States for Output and I/O Signals for Desktop Only
Configurations (Sheet 5 of 5)
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
GPIO[39:38]
GPIO[28:27]
SPI_MOSI
SPI_CS#
SPI_CLK
The states of Vcc3_3 signals are taken at the times During PLTRST# and Immediately after
PLTRST#.
The states of VccSus3_3 signals are taken at the times During RSMRST# and Immediately
after RSMRST#.
In S3
and interfaces may be powered when the ICH7 is in the S3
On the ICH7, PETp/n[4:1] are high until port is enabled by software. On the ICH7R and
ICH7DH, PETp/n[6:1] are high until port is enabled by software.
SLP_S5# signals will be high in the S4 state.
ICH7 drives these signals High after the processor Reset.
CPUPWRGD represents a logical AND of the ICH7’s VRMPWRGD and PWROK signals, and
thus will be driven low by the ICH7 when either VRMPWRGD or PWROK are inactive. During
boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition
from low to High-Z.
ICH7 drives these signals Low before PWROK rising and Low after the processor Reset.
Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset
HDBAR+08h:bit 0), at which time ACZ_RST# will be High and ACZ_BIT_CLK will be
Running.
GPIO18 will toggle at a frequency of approximately 1 Hz when the ICH7 comes out of reset
GPIO25 transitions from pulled high internally to actively driven within 100 ms of the
deassertion of the RSMRST# pin.
HOT
Intel
, signal states are platform implementation specific, as some external components
Suspend
Suspend
Suspend
®
Suspend
Suspend
Power
Plane
Core
Quick Resume Technology Interface (ICH7DH Only)
PLTRST#
RSMRST#
During
Input
High
High
Low
Low
Low
SPI Interface
1
2
/
Immediately
PLTRST#
RSMRST#
after
Input
High
High
Low
Low
Low
1
2
/
HOT
Defined
Defined
Driven
High
High
Low
S1
state.
S3
Defined
Defined
High
High
Low
COLD
Off
3
Defined
Defined
S4/S5
High
High
Low
Off
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