876784 Intel, 876784 Datasheet - Page 434

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

434
(Desktop
(Mobile/
Mobile
Only)
Only)
Ultra
7:6
Bit
3:1
8
5
4
4
0
Power Button Status (PWRBTN__STS) — R/WC. This bit is not affected by hard
resets caused by a CF9 write.
0 = If the PWRBTN# signal is held low for more than 4 seconds, the hardware clears
1 = This bit is set by hardware when the PWRBTN# signal is asserted Low,
NOTE: If the PWRBTN_STS bit is cleared by software while the PWRBTN# signal is
Reserved
Global Status (GBL _STS) — R/WC.
0 = The SCI handler should then clear this bit by writing a 1 to the bit location.
1 = Set when an SCI is generated due to BIOS wanting the attention of the SCI
Reserved
Bus Master Status (BM_STS) — R/WC. This bit will not cause a wake event, SCI or
SMI#.
0 = Software clears this bit by writing a 1 to it.
1 = Set by the Intel
NOTES:
1.
Reserved
Timer Overflow Status (TMROF_STS) — R/WC.
0 = The SCI or SMI# handler clears this bit by writing a 1 to the bit location.
1 = This bit gets set any time bit 22 of the 24-bit timer goes high (bits are numbered
the PWRBTN_STS bit, sets the PWRBTNOR_STS bit, and the system transitions to
the S5 state with only PWRBTN# enabled as a wake event.
This bit can be cleared by software by writing a one to the bit position.
independent of any other enable bit.
In the S0 state, while PWRBTN_EN and PWRBTN_STS are both set, an SCI (or
SMI# if SCI_EN is not set) will be generated.
In any sleeping state S1–S5, while PWRBTN_EN (PMBASE + 02h, bit 8) and
PWRBTN_STS are both set, a wake event is generated.
handler. BIOS has a corresponding bit, BIOS_RLS, which will cause an SCI and
set this bit.
memory. Bus master activity is detected by any of the PCI Requests being active,
any internal bus master request being active, the BM_BUSY# signal being active,
or REQ-C2 message received while in C3 or C4 state.
from 0 to 23). This will occur every 2.3435 seconds. When the TMROF_EN bit
(PMBASE + 02h, bit 0) is set, then the setting of the TMROF_STS bit will
additionally generate an SCI or SMI# (depending on the SCI_EN).
sell asserted, this will not cause the PWRBN_STS bit to be set. The PWRBTN#
signal must go inactive and active again to set the PWRBTN_STS bit.
If the BM_STS_ZERO_EN bit is set, then this bit will generally report as a 0.
LPC DMA (Mobile Only) and bus master activity will always set the BM_STS
bit, even if the BM_STS_ZERO_EN bit is set.
®
ICH7-M/ICH7-U when a bus master requests access to main
Description
LPC Interface Bridge Registers (D31:F0)
Intel
®
ICH7 Family Datasheet