876784 Intel, 876784 Datasheet - Page 498

• Manufacturer Part Number: 876784
• Manufacturer: Intel

Specifications of 876784

• Lead Free Status / RoHS Status: Compliant

12.1.15.2
12.1.16
12.1.17
498
AHCI Capable (Intel
Address Offset: 24h
Default Value:
This register allocates space for the memory registers defined in
ACHI capable ICH7 components (ICH7), this register is reserved and read only, unless
the SCRAE bit (offset 94h:bit 9) is set, in which case the register follows the definition
given in
NOTES:
1.
2.
SVID—Subsystem Vendor Identification Register
(SATA–D31:F2)
Address Offset: 2Ch
Default Value:
Lockable:
SID—Subsystem Identification Register (SATA–D31:F2)
Address Offset: 2Eh
Default Value:
Lockable:
31:10
15:0
15:0
9:4
2:1
Bit
Bit
Bit
3
0
.
Software is responsible for clearing this bit before entering combined mode.
The ABAR register must be set to a value of 0001_0000h or greater.
When the MAP.MV register is programmed for combined mode (00b), this register is RO.
Subsystem Vendor ID (SVID) — R/WO. Value is written by BIOS. No hardware
action taken on this value.
Subsystem ID (SID) — R/WO. Value is written by BIOS. No hardware action taken on
this value.
Section
Base Address (BA) — R/W. Base address of register memory space (aligned to 1 KB)
Reserved
Prefetchable (PF) — RO. Indicates that this range is not pre-fetchable
Type (TP) — RO. Indicates that this range can be mapped anywhere in 32-bit address
space.
Resource Type Indicator (RTE) — RO. Hardwired to 0 to indicate a request for register
memory space.
12.1.15.2.
00000000h
0000h
No
0000h
No
–
–
–
27h
2Fh
2Dh
®
ICH7R, ICH7DH, and Mobile Only)
SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Intel
R/W, RO
32 bits
R/WO
16 bits
Core
R/WO
16 bits
Core
Section
®
ICH7 Family Datasheet
12.3. For non-