ISP1760ETGA STEricsson, ISP1760ETGA Datasheet - Page 25

• Manufacturer Part Number: ISP1760ETGA
• Manufacturer: STEricsson

Specifications of ISP1760ETGA

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

CD00222702
Product data sheet
7.7 Overcurrent detection
The ISP1760 can implement a digital or analog overcurrent detection scheme. Bit 15 of
the HW Mode Control register can be programmed to select the analog or digital
overcurrent detection. An analog overcurrent detection circuit is integrated on-chip. The
main features of this circuit are self reporting, automatic resetting, low-trip time and low
cost. This circuit offers an easy solution at no extra hardware cost on the board. The port
power will automatically be disabled by the ISP1760 on an overcurrent event occurrence,
by de-asserting the PSWn_N signal without any software intervention.
When using the integrated analog overcurrent detection, the range of the overcurrent
detection voltage for the ISP1760 is 45 mV to 100 mV. Calculation of external components
should be based on the 45 mV value, with the actual overcurrent detection threshold
usually positioned in the middle of the interval.
For an overcurrent limit of 500 mA per port, a PMOS with R
is required. If a PMOS with a lower R
adjusted using a series resistor; see
ΔV
The digital overcurrent scheme requires using an external power switch with integrated
overcurrent detection, such as LM3526, MIC2526 (2 ports) or LM3544 (4 ports). These
devices are controlled by PSWn_N signals corresponding to each port. In the case of
overcurrent occurrence, these devices will assert OCn_N signals. On OCn_N assertion,
the ISP1760 cuts off the port power by de-asserting PSWn_N. The external integrated
power switch will also automatically cut off the port power in the case of an overcurrent
event, by implementing thermal shutdown. An internal delay filter will prevent false
Fig 7.
ΔV
I
OC(nom)
PMOS
PMOS
(1) R
= ΔV
Remark: To protect the OCn_N (n = 1, 2, 3) pins from Electrical OverStress (EOS), place R
1 kΩ on all the OCn_N (n = 1, 2, 3) pins. For details, refer to application note ISP1760; ISP1761
frequently asked questions (AN10054).
Adjusting analog overcurrent detection limit (optional) and EOS protection
= 1 μA
= voltage drop on PMOS
adj(oc)
trip(OC)
is optional.
= ΔV
Rev. 08 — 13 April 2010
5 V
trip(int)
− (I
REF5V
OC(nom)
Figure
DSon
ISP1760
× R
is used, analog overcurrent detection can be
7.
adj(oc)
Embedded Hi-Speed USB host controller
PSWn_N
), where:
I OC
004aaa662
R adj(oc) (1)
R EOS
OCn_N
DSon
V
of approximately 100 mΩ
BUS
© ST-ERICSSON 2010. All rights reserved.
ISP1760
25 of 105
EOS
of