ISP1760ETGA STEricsson, ISP1760ETGA Datasheet - Page 27

• Manufacturer Part Number: ISP1760ETGA
• Manufacturer: STEricsson

Specifications of ISP1760ETGA

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

CD00222702
Product data sheet
7.8.1 Hybrid mode
7.9 Power-On Reset (POR)
Table 6
Table 6.
In hybrid mode (see
transistor, controlled using one of the GPIO pins of the processor. This helps to reduce the
suspend current, I
V
back on, before the resume programming sequence starts.
Table 7
Table 7.
When V
t
1.2 V.
Voltage
V
V
Pins
DATA[31:0], A[17:1], TEST1, TEST2, TEST3,
TEST4, TEST5, TEST6, TEST7, DREQ,
DACK, IRQ, SUSPEND/WAKEUP_N
CS_N, RESET_N, RD_N, WR_N
PORP
Fig 10. Hybrid mode
CC(5V0)
CC(5V0)
CC(I/O)
, will typically be 800 ns. The pulse is started when V
shows the description of hybrid mode.
shows the status of output pins during hybrid mode.
CC(I/O)
is off during suspend, a 2 ms reset pulse is required when power is switched
The figure shows the LQFP pinout. For the TFBGA ballout, see
A 4.7 μF-to-10 μF electrolytic or tantalum capacitor is required on any one of the pins 5, 50 or 118.
All the electrolytic or tantalum capacitors must be of LOW ESR type (0.2 Ω to 2 Ω).
Hybrid mode
Pin status in hybrid mode
is directly connected to the RESET_N pin, the internal POR pulse width,
CC(I/O)
Figure
ISP1760BEUM
ISP1760BEGA
Rev. 08 — 13 April 2010
, below 100 μA. If the ISP1760 is used in hybrid mode and
10), V
10, 40, 48,
59, 67, 75,
5, 50, 118
104, 115
83, 94,
6, 7
CC(5V0)
85
9
V
V
REG1V8
REG1V8
REG3V3
CC(5V0)
CC(I/O)
10 µF
can be switched off using an external PMOS
V
on
on
off
on
off
controlled by the CPU
CC(I/O)
Embedded Hi-Speed USB host controller
Status
off
on
10 µF
100 nF
100 nF
004aaa677
100 nF
1.65 V to 3.6 V
V
on
off
X
X
X
CC(5V0)
100 nF
3.3 V to 5 V
CC(5V0)
Table
100 nF
2.
rises above V
© ST-ERICSSON 2010. All rights reserved.
ISP1760
normal
input
Status
high-Z
undefined
undefined
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