ISP1760ETGA STEricsson, ISP1760ETGA Datasheet - Page 46

• Manufacturer Part Number: ISP1760ETGA
• Manufacturer: STEricsson

Specifications of ISP1760ETGA

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Table 47.
[1]
CD00222702
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Force Hub Configuration register (address 0014h) bit allocation
8.3.10 Force Port Enable register
8.3.9 Force Hub Configuration register
31
23
15
R
R
R
R
0
0
0
7
0
Table 46.
The bit description of the register is given in
Table 48.
Write to bits 5 to 0 is enabled only when the FORCE_CONF bit in the Force Hub
Configuration register is set to logic 1. When bits 5 to 0 have values other than 00h, then
the corresponding port will automatically transition to the enabled state. The value of
bits 5 to 0 indicates the speed of the device attached to that port.
Bit
31 to 18
17 to 16
15 to 0
Bit
31 to 1
0
30
22
14
R
R
R
R
0
0
0
6
0
Symbol
-
FORCE_CONF Force Configured: On writing logic 1 to this bit, the hub will
Memory register (address 033Ch) bit description
Force Hub Configuration register (address 0014h) bit description
Symbol
-
MEM_BANK_
SEL[1:0]
START_ADDR
_MEM_READ
[15:0]
29
21
13
R
R
R
R
0
0
0
5
0
Rev. 08 — 13 April 2010
Description
reserved
immediately go to the configured state. The hub state will remain
unchanged on writing logic 0. When read, this field will always return 0.
Description
reserved
Memory Bank Select: Up to four memory banks can be selected.
For details on internal memory read description, see
Applicable to PIO mode memory read or write data transfers only.
Start Address for Memory Read Cycles: The start address for a
series of memory read cycles at incremental addresses in a
contiguous space. Applicable to PIO mode memory read data
transfers only.
reserved
28
20
12
R
R
R
R
0
0
0
4
0
reserved
reserved
reserved
[1]
[1]
[1]
[1]
Table
27
19
11
R
R
R
R
0
0
0
3
0
Embedded Hi-Speed USB host controller
47.
26
18
10
R
R
R
R
0
0
0
2
0
© ST-ERICSSON 2010. All rights reserved.
25
17
R
R
R
R
0
0
9
0
1
0
ISP1760
Section
FORCE_
CONF
R/W
7.3.1.
46 of 105
24
16
R
R
R
0
0
8
0
0
0