ISP1760ETGA STEricsson, ISP1760ETGA Datasheet - Page 92
ISP1760ETGA
Manufacturer Part Number
ISP1760ETGA
Description
Manufacturer
STEricsson
Datasheet
1.ISP1760ETGA.pdf
(105 pages)
Specifications of ISP1760ETGA
Package Type
TFBGA
Pin Count
128
Lead Free Status / RoHS Status
Compliant
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Product data sheet
14.2.1 Single cycle: DMA read
14.2 DMA timing
Table 100. Memory read
T
In the following sections:
Table 101. DMA read (single cycle)
T
Symbol
t
t
t
t
Symbol
V
t
t
t
t
t
t
t
V
t
t
t
d23
w13
su13
su23
a14
a24
d14
w14
a34
a44
h14
a14
a24
d14
amb
Fig 18. DMA read (single cycle)
amb
•
•
CC(I/O)
CC(I/O)
Polarity of DACK is active HIGH
Polarity of DREQ is active HIGH.
=
=
−
−
40
40
= 1.65 V to 1.95 V
= 3.3 V to 3.6 V
°
°
Parameter
data available time after RD_N HIGH
RD_N pulse width
CS_N set-up time before RD_N LOW
address set-up time before RD_N LOW
Parameter
DACK assertion time after DREQ assertion
RD_N assertion time after DACK assertion
data valid time after RD_N assertion
RD_N pulse width
DREQ de-assertion time after RD_N assertion
DACK de-assertion to next DREQ assertion time -
data hold time after RD_N de-asserts
DACK assertion time after DREQ assertion
RD_N assertion time after DACK assertion
data valid time after RD_N assertion
C to +85
C to +85
DREQ
DACK
RD_N
DATA
°
°
C; unless otherwise specified.
C; unless otherwise specified.
Rev. 08 — 13 April 2010
…continued
t
a14
t
a24
t
d14
t
w14
t
a34
Embedded Hi-Speed USB host controller
t
h14
t
a44
Min
-
21
0
0
Min
-
-
-
-
0
0
> t
0
0
d14
Max
1
-
-
-
Max
-
-
24
-
29
56
5
-
-
20
© ST-ERICSSON 2010. All rights reserved.
004aaa530
ISP1760
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
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ns
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92 of 105
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