ISP1760ETGA STEricsson, ISP1760ETGA Datasheet - Page 48

• Manufacturer Part Number: ISP1760ETGA
• Manufacturer: STEricsson

Specifications of ISP1760ETGA

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Table 51.
[1]
Table 53.
CD00222702
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Edge Interrupt Count register (address 0340h) bit allocation
DMA Start Address register (address 0344h) bit allocation
8.3.12 DMA Start Address register
R/W
R/W
R/W
R/W
31
23
15
31
23
W
W
0
0
0
7
0
0
0
Table 52.
This register defines the start address select for the DMA read and write operations. See
Table 53
Bit
31 to 24
23 to 16
15 to 0
R/W
R/W
R/W
R/W
30
22
14
30
22
W
W
0
0
0
6
0
0
0
for the bit allocation.
Edge Interrupt Count register (address 0340h) bit description
Symbol
MIN_WIDTH[7:0]
-
NO_OF_CLK[15:0] Number of Clocks: Count in number of clocks that the edge
R/W
R/W
R/W
R/W
29
21
13
29
21
W
W
0
0
0
5
0
0
0
Rev. 08 — 13 April 2010
Description
Minimum Width: Indicates the minimum width between two edge
interrupts in μSOFs (1 μSOF = 125 μs). This is not valid for level
interrupts. A count of zero means that interrupts occur as and
when an event occurs.
reserved
interrupt must be kept asserted on the interface. The default
value of these bits is 000Fh. 16 clocks of 30 MHz is
approximately 500 ns, which is the default IRQ pulse width.
NO_OF_CLK[15:8]
R/W
R/W
R/W
R/W
NO_OF_CLK[7:0]
MIN_WIDTH[7:0]
28
20
12
28
20
W
W
0
0
0
4
0
0
0
reserved
reserved
reserved
[1]
[1]
[1]
R/W
R/W
R/W
R/W
27
19
11
27
19
W
W
0
0
0
3
1
0
0
Embedded Hi-Speed USB host controller
R/W
R/W
R/W
R/W
26
18
10
26
18
W
W
0
0
0
2
1
0
0
© ST-ERICSSON 2010. All rights reserved.
R/W
R/W
R/W
R/W
25
17
25
17
W
W
0
0
9
0
1
1
0
0
ISP1760
R/W
R/W
R/W
R/W
48 of 105
24
16
24
16
W
W
0
0
8
0
0
1
0
0