ISP1760ETGA STEricsson, ISP1760ETGA Datasheet - Page 35

• Manufacturer Part Number: ISP1760ETGA
• Manufacturer: STEricsson

Specifications of ISP1760ETGA

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

[1]
Table 21.
[1]
CD00222702
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
The reserved bits should always be written with the reset value.
CONFIGFLAG - Configure Flag register (address 0060h) bit allocation
8.2.5 CONFIGFLAG register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
23
15
31
23
15
0
0
7
0
0
0
0
7
0
reserved
Table 20.
[1]
The bit allocation of the Configure Flag (CONFIGFLAG) register is given in
Bit
31 to 14
13 to 0
For details on register bit description, refer to
Universal Serial Bus Rev.
[1]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
22
14
30
22
14
0
0
6
0
0
0
0
6
0
Symbol
-
FRINDEX
[13:0]
FRINDEX - Frame Index register (address: 002Ch) bit description
R/W
R/W
R/W
R/W
R/W
R/W
R/W
21
13
29
21
13
0
0
5
0
0
0
0
5
0
Description
reserved
Frame Index: Bits in this register are used for the frame number in the SOF
packet and as the index into the frame list. The value in this register
increments at the end of each time frame. For example, microframe.
Rev. 08 — 13 April 2010
1.0”.
reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
20
12
28
20
12
[1]
0
0
4
0
0
0
0
4
0
FRINDEX[7:0]
reserved
reserved
reserved
reserved
[1]
Ref. 2 “Enhanced Host Controller Interface Specification for
[1]
[1]
[1]
[1]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
19
11
27
19
11
FRINDEX[13:8]
0
0
3
0
0
0
0
3
0
Embedded Hi-Speed USB host controller
R/W
R/W
R/W
R/W
R/W
R/W
R/W
18
10
26
18
10
0
0
2
0
0
0
0
2
0
© ST-ERICSSON 2010. All rights reserved.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
17
25
17
0
9
0
1
0
0
0
9
0
1
0
ISP1760
Table
R/W
R/W
R/W
R/W
R/W
R/W
R/W
21.
CF
35 of 105
16
24
16
0
8
0
0
0
0
0
8
0
0
0