ISP1760ETGA STEricsson, ISP1760ETGA Datasheet - Page 58

• Manufacturer Part Number: ISP1760ETGA
• Manufacturer: STEricsson

Specifications of ISP1760ETGA

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

CD00222702
Product data sheet
Multiple transfers are scheduled to the shared memory for various endpoints by traversing
the next link pointer provided by endpoint data structures, until it reaches the end of the
endpoint list. There are three endpoint lists: one for ISO endpoints, and the other for INTL
and ATL endpoints. If the schedule is enabled, the host controller executes the ISO
schedule, followed by the INTL schedule, and then the ATL schedule.
These lists are traversed and scheduled by the software according to the EHCI traversal
rule. The host controller executes scheduled ISO, INTL and ATL PTDs. The completion of
a transfer is indicated to the software by the interrupt that can be grouped under various
PTDs by using the AND or OR registers that are available for each schedule type: ISO,
INTL and ATL. These registers are simple logic registers to decide the completion status
of group and individual PTDs. When the logical conditions of the Done bit is true in the
shared memory, it means that PTD has completed.
There are four types of interrupts in the ISP1760: ISO, INTL, ATL and SOF. The latency
can be programmed in multiples of μSOF (125 μs).
Rev. 08 — 13 April 2010
Embedded Hi-Speed USB host controller
© ST-ERICSSON 2010. All rights reserved.
ISP1760
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