SCD128410QCE Intel, SCD128410QCE Datasheet - Page 32

• Manufacturer Part Number: SCD128410QCE
• Manufacturer: Intel

Specifications of SCD128410QCE

• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
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Figure 3. CD1284 Functional Block Diagram
Figure 4. Internal Address Generation
ADDRESS
INTERFACE
AND DMA
CPU
LOGIC
BUS
The serial data channels are made of ‘bit engines’ that off-load the task of receiving and
transmitting each bit from the MPU. When receiving data and after processing a complete bit, the
bit engines interrupt the MPU so that it can perform the next required task. For example, the MPU
takes the bit and adds it to a character being assembled. When transmitting, it sends the bit engine
the next bit of the character being transmitted. The MPU is not concerned with basic bit timing; this
task is handled by the bit engines, leaving the MPU free to perform higher-level processing, such as
detecting special characters.
CAR
INTERRUPT
LOGIC
ROM
MPU
GENERATION
ADDRESS
PORT FIFO
PARALLEL
RAM
RAM REGISTER
CONTROL STATE
ARRAY
MACHINE
CHANNEL 2 REGISTERS
CHANNEL 3 REGISTERS
PARALLEL PORT
(CHANNEL 0)
PORT LOGIC
REGISTERS
LOGIC AND BIT
LOGIC AND BIT
PARALLEL
CHANNEL 2
CHANNEL 3
TIMING
TIMING
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