SCD128410QCE Intel, SCD128410QCE Datasheet - Page 94

• Manufacturer Part Number: SCD128410QCE
• Manufacturer: Intel

Specifications of SCD128410QCE

• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
6.3
6.3.1
6.3.1.1
94
fifo thresh = 8 */
commands */
commands */
CCR */
}
Serial Poll Mode Examples
The CD1284 provides a set of seven registers dedicated to Poll-mode operation, described in
Chapter
service requests from any of the channels receiver, transmitter, or modem signal change functions.
The primary registers involved in polling are: SVRR, RIR, TIR, MIR, and CAR. The
supplementary registers are: RIVR, TIVR, and MIVR. Of the latter three registers, only RIVR is
actually used. RIVR provides the service request status for ‘good’ data or exception data. The
TIVR and MIVR provide redundant information and are rarely used. Other registers related to
service requests (TDR, RDSR, MISR, and so on) perform the same functions as in hardware-
acknowledged service requests. The parallel channel uses a slightly different register manipulation
procedure and is shown separately. The top-level polling routine is the same regardless of the type
of request serviced.
Once again, C code fragments describe the functions. As with other coding examples, it is assumed
that register addresses are defined elsewhere, such as in a header file. The routines cannot be
considered complete. The routines cannot be considered complete; some pieces are dependent on
the system software design and the code presented is only an example. The pieces do, however,
show methods used to implement the poll mode service request/service acknowledge sequence.
Polling Routine Examples
Scanning Loop
/* Poll-mode code fragments routinely check for any servicing requests and branches
to the appropriate service routine. The code prioritizes service requests as receive,
transmit, modem and parallel, in that order. System design dictates the actual
priorities required. Note that the routine ignores the state of the DMA active bit.
*/
poll( )
{
5.0. This section shows one of many ways that these registers are used to detect and
outportb(CAR, chan);
outportb(RTPR, 0x14); /* set channel time-out value (20ms) */
outportb(TCOR, 0x01); /* constants for 25 MHz clock – clock option*/
outportb(TBPR, 0x51); /*
outportb(RCOR, 0x01); /* constants for 25 MHz clock – clock option*/
outportb(RBPR, 0x51); /*
outportb(COR1, 0x03); /* no parity, 1 stop bit, 8 bit chars */
outportb(COR2, 0x40); /* auto. in-band flow control */
outportb(COR3, 0x38); /* transp. flow-control, special char 1 & 2 detect,
while (inportb(CCR) != 0)/* make sure that CCR is zero before issuing
outportb(CCR, 0x4E);
outportb(COR5, 0x80); /* enable ISTRIP */
outportb(SRER, 0x14); /* enable receive and transmit interrupts */
while (inportb(CCR) != 0)/* make sure that CCR is zero before issuing
outportb(CCR, 0x1A);
char
char
if (status = inportb(SVRR) & 0x0F) {/* Mask off DMA status */
;
;
status;
rx_stat = tx_stat = md_stat = 0, par_stat = 0;
/* set channel number in CAR */
/* issue COR changed command for COR1, 2, 3 */
/* issue receiver and transmitter enable command to
– baud rate period */
– baud rate period */
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