SCD128410QCE Intel, SCD128410QCE Datasheet - Page 50

• Manufacturer Part Number: SCD128410QCE
• Manufacturer: Intel

Specifications of SCD128410QCE

• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
5.5.1
50
Channel service needs, such as an empty transmit FIFO, are indicated to the CPU by one of three
service-request indicators: one for all receivers, one for all transmitters, and one for all modem
signal changes. The internal processor (MPU) scans each channel sequentially for service needs,
posting a request when it detects a particular type. It continues the Fair Share scheme used in the
external daisy-chain configuration by not allowing a channel to post another request of one type
until all other channels have posted their requests of that type, if any. For example, if channel two is
currently being serviced for a transmit request and channel three has one pending, the request from
channel three is posted before channel two is able to make another request for transmit service.
Each receiver and transmitter has a 12-character FIFO. The receiver has two additional character
holding locations: the Receive Character Holding and Receiver Shift registers. The transmitter also
has two additional locations, the Transmitter Holding and Transmitter Shift registers. The receive
FIFO has a programmable threshold that sets the level at which a service request is posted. When
data reaches this FIFO-full threshold, a request is made of the CPU to empty the FIFO (for details
see
the DTR output to be deasserted (see the flow-control description).
In the asynchronous serial data protocol, a message consists of one ‘character,’ made up of bits,
either high or low, representing a ‘1’ or ‘0’ value. A character can be from five to eight bits plus an
optional parity bit bracketed by a start bit and a stop bit. Each bit has a time duration that sets the
data transmission rate — or baud rate. The start bit indicates the beginning of a character bitstream
and is indicated by a transition from a logic ‘1’ to a logic ‘0’ (mark to space) on the transmission
media. The start bit lasts one ‘bit-time’ and is immediately followed by the data bits (8:5), the
parity if any, and the stop bit.
As previously discussed, the CD1284 incorporates special hardware to receive and transmit each
bit. These are the ‘bit engines’. They perform all timing associated with sending or receiving one
serial data bit. A bit engine behaves differently depending on whether it is sending or receiving.
When a complete bit is received, the bit engine interrupts the MPU so that it can handle the bit on
the character level. This usually entails its addition to the character being assembled. For
transmitting, a transmit bit engine interrupt causes the MPU to give it the next bit to transmit. The
bit engine interrupt occurs at the end of a bit time that is timed by the engine, thus removing that
duty from the MPU.
Receiver Operation
Each channel can be programmed to receive characters with several different parameters, such as
character length, parity, number of stop bits, FIFO threshold, and baud rate. Each receiver is
independent of any other receiver. It can also be set to a different baud rate from its corresponding
transmitter.
Before valid data can be received, the CPU must set up each channel by programming the desired
operational parameters in the COR1–COR5, the BRRR, RCOR, and RBPR. Once these registers
are set, the channel is enabled by issuing the receiver enable command through the CCR and
enabling service requests in the SRER.
Once a receiver is enabled, its bit engine begins to scan the RxD input for a valid start bit. It does
this by detecting a falling edge transition on the input. When the transition is detected, the bit
engine delays until the middle of the programmed bit time and rechecks the input. If the input is
still low, the start bit is considered valid and character assembly begins. At each subsequent full bit
time, the input is checked and its level recorded as the value of the next bit. If, at the center of the
bit time, the RxD input returns to a mark state, then the start bit is considered invalid and the bit
engine returns to the start bit detect mode.
Section
5.5.1). Receive FIFOs also have a programmable threshold that, when reached, causes
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