SCD128410QCE Intel, SCD128410QCE Datasheet - Page 6

• Manufacturer Part Number: SCD128410QCE
• Manufacturer: Intel

Specifications of SCD128410QCE

• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
6
7.6
7.7
7.8
7.9
7.5.8
Special Character Registers ............................................................................. 133
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
7.6.7
7.6.8
7.6.9
7.6.10 Transmit Clock Option Register ........................................................... 136
Channel Registers — Parallel Pipeline ............................................................. 136
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.7.6
7.7.7
7.7.8
7.7.9
7.7.10 Parallel FIFO Fill Pointer Register........................................................ 142
7.7.11 Parallel FIFO Holding Register 1.......................................................... 142
7.7.12 Parallel FIFO Holding Register 2.......................................................... 142
7.7.13 Parallel FIFO Quantity Register ........................................................... 143
7.7.14 Parallel FIFO Status Register............................................................... 143
7.7.15 Parallel FIFO Threshold Register......................................................... 144
7.7.16 Run Length Count Register.................................................................. 144
7.7.17 Stale Data Timer Count Register ......................................................... 145
7.7.18 Stale Data Timer Period Register......................................................... 145
Channel Registers — Parallel Port ................................................................... 146
7.8.1
7.8.2
7.8.3
7.8.4
7.8.5
7.8.6
7.8.7
7.8.8
7.8.9
7.8.10 Parallel Channel Interrupt Status Register ........................................... 150
7.8.11 Parallel Configuration Register............................................................. 151
7.8.12 Special Command Register.................................................................. 152
7.8.13 Short Pulse Register ............................................................................ 153
Pin Control Registers ........................................................................................ 154
7.9.1
7.9.2
Receive Timeout Period Register......................................................... 133
Special Character Register 1 ............................................................... 133
Special Character Register 2 ............................................................... 133
Special Character Register 3 ............................................................... 134
Special Character Register 4 ............................................................... 134
Received Character Range Detection.................................................. 134
Special Character Range — High ........................................................ 134
Special Character Range — Low ......................................................... 134
Serial Service Request Enable Register .............................................. 135
Transmit Baud Rate Period Register.................................................... 135
Data Error Register .............................................................................. 136
DMA Buffer Data Register — High....................................................... 137
DMA Buffer Data Register — Low........................................................ 137
Firmware Revision Code Holding Register Status Register................. 138
Local Interrupt Vector Register ............................................................ 138
Parallel Auxiliary Control Register........................................................ 139
Parallel Channel Reset Register .......................................................... 140
Parallel FIFO Control Register ............................................................. 140
Parallel FIFO Empty Pointer Register .................................................. 141
EPP Address Register ......................................................................... 146
Host Timeout Value Register ............................................................... 146
Input Value Register............................................................................. 147
Manual Data Register .......................................................................... 148
Negotiation Enable Register ................................................................ 148
Negotiation Status Register ................................................................. 148
Ones Detect Register ........................................................................... 149
Output Value Register .......................................................................... 150
Parallel Channel Interrupt Enable Register .......................................... 150
Signal Status Register.......................................................................... 154
Zeros Detect Register .......................................................................... 154
Datasheet