SCD128410QCE Intel, SCD128410QCE Datasheet - Page 39

• Manufacturer Part Number: SCD128410QCE
• Manufacturer: Intel

Specifications of SCD128410QCE

• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

5.3.2.2
5.3.2.3
5.3.2.4
Datasheet
Another use for these bits is channel encoding. This is applicable in a single-CD1284 design and
any design not using daisy-chaining (requiring a unique address range for each device). This
applies where the value in the LIVR as a vector for a hardware interrupt response is not necessary.
Since each channel has its own LIVR, these five bits have a unique value identifying the channel.
There is no need to read the RICR, TICR, or MICR to find the channel number; in a single I/O
operation, the CPU determines both the type of interrupt and the number of the channel requesting
service. With five bits available, systems with small numbers of CD1284s are able to encode both
the channel number and chip identification number in the LIVR.
Once the acknowledge procedure is complete, the CD1284 is ready to be serviced for the type of
interrupt acknowledged. For example, if the interrupt was for receive good data, the CPU would
read the RDCR to determine the number of characters available in the receive FIFO. It then reads
the same number of characters, by successive reads, from the RDSR. Other tasks, such as disabling
future interrupts or changing channel parameters, could also be performed at this time.
Once all tasks involved in servicing the interrupt are complete, one more operation is performed.
To inform the CD1284 that the service acknowledge is complete, the CPU writes a dummy value to
the EOSRR. Although the data written does not matter, the write operation is important. This write
forces the internal context switch back to normal operating mode.
Summary of Interrupt Driven Service Requests, Serial Channels
The actions that occur during an interrupt request/service are:
Common Service Acknowledge
One method of hardware-activated, service-acknowledge request is the common service
acknowledge. In this method, all SVCACKx* inputs are tied together and are driven from the same
source. In this configuration, the CD1284 internally prioritizes the acknowledge as receive,
transmit, parallel, and modem. If a device has both a receive and a parallel request pending, the
common acknowledge causes it to respond with the vector for the receiver. Then a subsequent
service acknowledge allows the parallel channel request to be serviced.
Software-Activated Context Switch — Serial Channels
It is possible, by CPU manipulation of some internal registers, to cause the context switch without
activating any of the SVCACK* hardware inputs. The method is the same used in the poll-mode–
CD1284 design. Once the CPU has detected the service request through its interrupt response
circuitry, it follows the same procedures that a polling method uses when it detects an active
service request. Refer to the context switching description in the following section.
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The CPU senses service request from one of the CD1284 service-request outputs through its
interrupt request input.
The CPU responds by performing a read cycle to activate the appropriate SVCACK* input
pin.
The CPU decodes the value read from the vector register during step 2, and decides on the type
of service request (if necessary).
The CPU reads the R/T/M/ICR to determine the channel number.
The CPU services the request (load transmit FIFO, read receive FIFO, and so on).
The CPU writes a dummy value to the EOSRR to terminate the service routine.
IEEE 1284-Compatible Parallel Interface Controller — CD1284
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