LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 18

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LSI53CF92A-64QFP

Manufacturer Part Number
LSI53CF92A-64QFP
Description
Manufacturer
LSI
Datasheet

Specifications of LSI53CF92A-64QFP

Lead Free Status / RoHS Status
Supplier Unconfirmed
Figure 1.1
A2-DBRD/
1-4
RESET
MODE
Processor
DMA Bus
8-Bit Host
A3-ALE
DBWR/
DACK/
CLK
INT/
DREQ
WR/
RD/
CS/
9-Bit
A1
A0
Bus
Functional Block Diagram
Figure 1.1
Introduction
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
CLK Conversion
24-Bit Transfer Count
Registers 1–4
Configuration
Destination ID
Sync Offset
Read/Write Control
Sync Period
Command
Time Out
Register
illustrates the functional block diagram for the LSI53CF92A.
FIFO (16 x 9-Bit)
Sequencer
Transfer
Counter
24-Bit
Seq. Mode
Seq. Mode
Parity Generator
Steering Logic
and Checker
Sequence
Register
Interrupt
Register
Status
Step
Drivers
Control
48 mA
SCSI
SCSI
Data/Control
Bus

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