LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 28

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.4 Host Bus Configuration
2.4.1 Mode Description
2.4.2 Multiplexed Bus Configuration Mode
2-8
If parity test mode is enabled during a DMA transfer, DBP is a duplicate of
DB7. This is true both for data flowing from the FIFO to the SCSI Data Bus
(SDB) pins or data flowing from the FIFO to the Host Data Bus (DB) pins.
The FSC flags parity errors as data comes into the FIFO from the SCSI
bus, or as it leaves the FIFO on its way out to the SCSI bus.
The DMA and microprocessor buses may be configured in one of the two
following ways.
Multiplexed
Nonmultiplexed Dual bus; 8-bit DMA bus and 8-bit nonmultiplexed processor bus.
The operating mode is selected by the Mode strapping pin; refer to
Chapter 3, “Signal Descriptions,”
operating modes are labeled Multiplexed mode and Nonmultiplexed
mode. Refer to
configuration diagrams. Both of these dual bus modes have separate
data buses for DMA and microprocessor, which may be active
simultaneously provided CS/ is not accessing the FIFO.
In this dual-bus mode, 8-bit operations are supported by the DMA Data
bus. The microprocessor interface is supported by the PAD bus. FIFO
parity is not available for data transfers over the PAD bus. The direction
of transfer is determined by the RD/ and WR/ lines. CS/ must be active
during PAD bus accesses.
In the Multiplexed Bus Configuration mode, register addresses and register
data are multiplexed on the PAD bus. The register address on the PAD[3:0]
lines is latched into the chip on the HIGH to LOW transition of ALE (A3).
In this bus configuration mode, the Data bus configuration is for 8-bit
DMA transfers. Pin A2 functions as the Data bus read signal (DBRD/),
which drives the DMA read data. A1 and A0 must be tied to ground.
Functional Description
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Chapter 1, “Introduction,” Figure 1.2,
Dual bus; 8-bit DMA bus and 8-bit multiplexed processor
address/data bus.
for the setting of either mode. The two
and
Figure 1.3
for