LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 64

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

4-14
Register: 0x05
Interrupt
Read Only
Register Bank 0 or 1
This 8-bit register is used in conjunction with the
Sequence Step
this register when the interrupt output is true clears all three registers. The
entire Interrupt register is cleared (0x00) by a hardware reset or the Reset
command, but not SCSI reset. The default value of this register is 0x00.
SRST
ILCMD
DIS
Registers
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
SRST
7
0
Note:
ILCMD
6
0
This register should only be read when an interrupt is
pending. The
be read prior to reading this register.
SCSI Reset Detected
This bit is set if SCSI Reset Reporting is enabled in the
Configuration 1 (Config 1)
reset on the SCSI bus.
Illegal Command
This bit is set when a reserved code is placed in the
Command
group different than the mode the FSC is currently in.
Refer to the
generated when this bit is set.
Disconnect
In initiator mode, this bit is set when the target
disconnects or a Selection or Reselection time-out
occurs. When the FSC is in target mode, this bit is set if
a Terminate Sequence or Command Complete Sequence
command causes the FSC to disconnect from the bus.
register to determine the cause of an interrupt. Reading
DIS
5
0
register or when the command is from a mode
Sequence Step
Command
BS
4
0
Default
FC
register definition. An interrupt is
3
0
register and the chip detects a
and
RESEL
Status
2
0
Status
registers should
register and
1
0
SI
0
0
7
6
5