LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 26

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.2.3 Bus-Initiated Reset
2.2.4 Stacked Commands
2.3 Parity Checking and Generation
2-6
The FSC prevents the target from disconnecting by holding ACK/
asserted on the bus while the microprocessor examines the Bus ID and
Identify message bytes. The Message Accept command causes the FSC
to release ACK/. Any further message bytes can be received with the
Transfer Information command.
A SCSI bus-initiated reset is recognized by the FSC at any time. When
SCSI RST/ pulses true, the FSC disconnects from the bus and resets its
internal sequencer. If bit 6 in
set, the FSC generates a SCSI reset-detected interrupt.
The
gives commands to the FSC. If DMA commands are to be stacked, the
Transfer Count must be loaded prior to loading the respective command.
Command stacking should only be used during Data In and Data Out. If
stacked commands are used in Initiator mode, it is recommended that the
Features Enable bit in the
causes the SCSI phase lines to be latched at the end of a command.
The FSC has three bits that control parity generation and checking.
These three bits can be accessed by the user and are described in
Table
parity errors. In this document, the word detected in conjunction with
parity error should be understood to imply that parity checking has
previously been enabled.
In Target role, detected parity errors set the Parity Error bit (bit 5 in the
Status
interrupt. In Initiator role, detected parity errors set the Parity Error bit
and, if receiving SCSI bytes, assert ATN/ (Attention) prior to releasing
Functional Description
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Note:
Command
2.1. If parity checking is disabled, the FSC does not check for
register) and clear the
The settings of the SCSI-2 or Queue Tag Enable bits do not
affect this operation.
register is a two-deep, eight-bit read/write register that
Configuration 2 (Config 2)
Configuration 1 (Config 1)
Command
register without causing an
register be set. This
register is not