LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 55

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Register: 0x00–0x01
Transfer Counter
Read Only
Register Bank 0 or 1
These registers combine with the
(0x0E) to form a 24-bit transfer counter. A read from these addresses
returns the value currently in the counter. DMA commands use the
counter to terminate a transfer. When the counter decrements to zero,
the Terminal Count bit in the
transfer is complete. Any DMA command loads the transfer count into the
counter. A DMA NOP (0x80) loads the counter while the non-DMA NOP
(0x00) does not.
During SCSI Data phases, the transfer counter decrements on the
leading edge of the following:
* In DMA Burst mode, the transfer counter decrements on the leading
edge of RD/, DBRD/, DBWR/, and DACK/ as follows:
Standard Register Set
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
7
0
Target Decremented by
–
–
Initiator Decremented by
–
–
–
Target Decremented by
–
–
Initiator Decremented by
–
–
Data In phase DACK/ *
Data Out phase REQ/
Synchronous Data In DACK/ *
Asynchronous Data In ACK/
Data Out DACK/ *
Message In, Status DACK/ *
Message Out, Command REQ/
Message In, Status ACK/
Message Out, Command DACK/ *
6
0
5
0
Status
4
0
Default
Transfer Counter High/ID
register is set, indicating the current
3
0
2
0
1
0
register
0
0
4-5