LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 51

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Chapter 4
Registers
This chapter contains descriptions of all FSC registers. A register map is
provided in
hexadecimal. The terms set and assert refer to bits that are programmed
to binary one. Similarly, the terms reset, clear, or deassert refer to bits
that are programmed to binary zero. Some FSC registers have different
meanings during reads than writes. When CS/ is true, the register being
accessed is determined by either RD/ or WR/ together with the address
pins A[3:0] and the state of the Register Bank Select bit (bit 3 in the
Configuration 4 (Config 4)
either CS/ or DACK/ together with RD/ or WR/. Address pins A[3:0] are
ignored when DACK/ is active, but must be driven when CS/ is active.
The FSC registers must not be read while they are in transition,
especially the FIFO,
This chapter contains the following sections:
LSI53CF92A Fast SCSI Controller
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Section 4.1, “Standard Register Set”
Section 4.2, “SCAM Register Set”
Appendix A, “Register Map.”
FIFO
register). The FIFO may be accessed using
Flags, and
Transfer Counter
All register values are given in
registers.
4-1