LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 92

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

4-42
Register: 0x0E
SCSI Output Data Latch (SODL)
Read/Write
Register Bank 1
SD[7:0]
Register: 0x0F
SCSI Bus Data Lines (SBDL)
Read Only
Register Bank 1
SD[7:0]
Registers
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
SD7
SD7
7
0
7
x
SD6
SD6
x
0
(Bit Set = Assert SCSI Data Bit)
This register provides low-level control of the SCSI bus
data signals. This register is cleared by the Reset Chip
command, assertion of the RESET pin, a SCSI Bus
reset, chip power-up, and held reset whenever the Low
Level mode bit is cleared. The contents of this register
are placed onto the SCSI bus during low-level arbitration
(ARB bit set) or by setting the Assert Data Bus bit in the
SCSI Control (SCONTROL)
(SCSI Data Bits, Active High)
This read only register provides status of the SCSI bus
data signals. These bits are not latched; they are a true
representation of what is on the SCSI bus at the time this
register is read.
SD5
SD5
x
0
SD4
SD4
x
0
Default
Default
SD3
SD3
x
0
register.
SD2
SD2
x
0
SD1
SD1
x
0
SD0
SD0
0
x
[7:0]
[7:0]
0
0