MC9S12XDT512MAA Freescale, MC9S12XDT512MAA Datasheet - Page 1013

• Manufacturer Part Number: MC9S12XDT512MAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512MAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

PPSP[7:0]
PIEP[7:0]
Reset
Reset
Field
24.0.5.40 Port P Interrupt Enable Register (PIEP)
Read: Anytime.
Write: Anytime.
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated
with Port P.
Field
24.0.5.41 Port P Interrupt Flag Register (PIFP)
Read: Anytime.
Write: Anytime.
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling
edge based on the state of the PPSP register. To clear this flag, write logic level “1” to the
corresponding bit in the PIFP register. Writing a “0” has no effect.
7–0
7–0
W
W
R
R
PIEP7
PIFP7
Polarity Select Port P
0 Falling edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-up device is
1 Rising edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-down device
Interrupt Enable Port P
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
7
0
7
0
connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used
as input.
is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is
used as input.
PIEP6
PIFP6
0
0
6
6
Figure 24-42. Port P Interrupt Enable Register (PIEP)
Figure 24-43. Port P Interrupt Flag Register (PIFP)
Table 24-38. PPSP Field Descriptions
Table 24-39. PIEP Field Descriptions
PIEP5
PIFP5
5
0
5
0
PIEP4
PIFP4
0
0
4
4
Description
Description
PIEP3
PIFP3
3
0
3
0
PIEP2
PIFP2
0
0
2
2
PIEP1
PIFP1
1
0
1
0
PIEP0
PIFP0
0
0
0
0