MC9S12XDT512MAA Freescale, MC9S12XDT512MAA Datasheet - Page 618
MC9S12XDT512MAA
Manufacturer Part Number
MC9S12XDT512MAA
Description
Manufacturer
Freescale
Datasheet
1.MC9S12XDT512MAA.pdf
(1348 pages)
Specifications of MC9S12XDT512MAA
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
32KB
# I/os (max)
59
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XDT512MAA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 17 Memory Mapping Control (S12XMMCV2)
The MMCCTL0 register is used to control external bus functions, i.e., availability of chip selects.
618
CS[3:0]E
Field
3–0
Chip Select Enables — Each of these bits enables one of the external chip selects CS3, CS2, CS1, and CS0
outputs which are asserted during accesses to specific external addresses. The associated global address
ranges are shown in
Chip selects are only active if enabled in normal expanded mode, Emulation expanded mode and special test
mode. The function disabled in all other operating modes.
0 Chip select is disabled
1 Chip select is enabled
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
1
When the internal NVM is enabled (see ROMON in
Register
memory block.
(MMCCTL1)”) the CS0 is not asserted in the space occupied by this on-chip
Global Address Range
0x00_0800–0x0F_FFFF
0x10_0000–0x1F_FFFF
0x20_0000–0x3F_FFFF
0x40_0000–0x7F_FFFF
Table 1-6
Table 17-4. MMCCTL0 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 17-5. Chip Select Signals
and
Table 1-21
CAUTION
and
Description
Figure
Section 1.3.2.5, “MMC Control
1-23.
Asserted Signal
CS0
CS3
CS2
CS1
1
Freescale Semiconductor
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