MC9S12XDT512MAA Freescale, MC9S12XDT512MAA Datasheet - Page 151

• Manufacturer Part Number: MC9S12XDT512MAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512MAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

4.3.2.16
The A/D conversion results are stored in 16 read-only result registers. The result data is formatted in the
result registers bases on two criteria. First there is left and right justification; this selection is made using
the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using
the DSGN control bit in ATDCTL5. Signed data is stored in 2’s complement format and only exists in left
justified format. Signed data selected for right justified format is ignored.
Read: Anytime
Write: Anytime in special mode, unimplemented in normal modes
4.3.2.16.1
Freescale Semiconductor
R (10-BIT)
R (10-BIT)
R (8-BIT)
R (8-BIT)
Reset
Reset
W
W
Figure 4-18. Left Justified, ATD Conversion Result Register x, High Byte (ATDDRxH)
Figure 4-19. Left Justified, ATD Conversion Result Register x, Low Byte (ATDDRxL)
BIT 9 MSB
BIT 7 MSB
ATD Conversion Result Registers (ATDDRx)
Left Justified Result Data
BIT 1
u
0
7
0
7
= Unimplemented or Reserved
= Unimplemented or Reserved
BIT 0
BIT 8
BIT 6
u
0
6
0
6
MC9S12XDP512 Data Sheet, Rev. 2.21
BIT 7
BIT 5
0
0
0
5
0
5
Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description
BIT 6
BIT 4
0
0
0
4
0
4
BIT 5
BIT 3
3
0
0
0
0
3
u = Unaffected
BIT 4
BIT 2
0
0
0
0
2
2
BIT 3
BIT 1
0
0
0
1
1
0
BIT 2
BIT 0
0
0
0
0
0
0
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