MC9S12XDT512MAA Freescale, MC9S12XDT512MAA Datasheet - Page 791

• Manufacturer Part Number: MC9S12XDT512MAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512MAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

21.3.2.2
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
This register is used to configure the external access stretch (wait) function.
Freescale Semiconductor
EXSTR[2:0]
EWAITE
Reset
Field
2–0
7
W
R
EWAITE
External Wait Enable — This bit enables the external access stretch function using the external EWAIT input
pin. Enabling this feature may have effect on the minimum number of additional stretch cycles (refer to
Table
External wait feature is only active if enabled in normal expanded mode and emulation expanded mode; function
not available in all other operating modes.
0 External wait is disabled
1 External wait is enabled
External Access Stretch Bits 2, 1, 0 — This three bit field determines the amount of additional clock stretch
cycles on every access to the external address space as shown in
cycles depends on the EWAITE setting.
Stretch cycles are added as programmed in normal expanded mode and emulation expanded mode; function
not available in all other operating modes.
External Bus Interface Control Register 1 (EBICTL1)
0
7
21-6).
Figure 21-4. External Bus Interface Control Register 1 (EBICTL1)
= Unimplemented or Reserved
EXSTR[2:0]
0
0
000
001
010
011
100
101
110
111
6
Table 21-6. External Access Stretch Bit Definition
Table 21-5. EBICTL1 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
EWAITE = 0
2 cycles
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
8 cycles
1 cycle
0
0
4
Number of Stretch Cycles
Description
0
0
3
Chapter 21 External Bus Interface (S12XEBIV2)
Table
EWAITE = 1
>= 2 cycles
>= 2 cycles
>= 3 cycles
>= 4 cycles
>= 5 cycles
>= 6 cycles
>= 7 cycles
>= 8 cycles
EXSTR2
21-6. The minimum number of stretch
1
2
EXSTR1
1
1
EXSTR0
1
0
793