MC9S12XDT512MAA Freescale, MC9S12XDT512MAA Datasheet - Page 699

• Manufacturer Part Number: MC9S12XDT512MAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512MAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

19.3.1.3
Read: Anytime
Write: Bits 7:6 only when DBG is neither secure nor armed.
Freescale Semiconductor
TRCMOD[3:2]
TRANGE[5:4]
TALIGN[1:0]
0x0022
TSOURCE
Reset
Field
7–6
5–4
3–2
1–0
W
R
Bits 5:0 anytime the module is disarmed.
Debug Trace Control Register (DBGTCR)
0
Trace Source Control Bits — The TSOURCE bits select the data source for the tracing session. If the MCU
system is secured, these bits cannot be set and tracing is inhibited. See
Trace Range Bits —The TRANGE bits allow filtering of trace information from a selected address range when
tracing from the CPU in detail mode. The XGATE tracing range cannot be narrowed using these bits. To use a
comparator for range filtering, the corresponding COMPE and SRC bits must remain cleared. If the COMPE bit
is not clear then the comparator will also be used to generate state sequence triggers or tags. If the SRC bit is
set the comparator is mapped to the XGATE busses, corrupting the trace. See
Trace Mode Bits — See
mode, change of flow information is stored. In loop1 mode, change of flow information is stored but redundant
entries into trace memory are inhibited. In detail mode, address and data for all memory and register accesses
is stored. See
Trigger Align Bits — These bits control whether the trigger is aligned to the beginning, end or the middle of a
tracing session. See
7
TSOURCE
1
2
TRANGE
No range limitations are allowed. Thus tracing operates as if TRANGE = 00.
No detail mode tracing supported. If TRCMOD =10, no information is stored.
00
01
10
0
Table 19-11
6
TSOURCE
Figure 19-5. Debug Trace Control Register (DBGTCR)
Table 19-9. TSOURCE Trace Source Bit Encoding
11
10
00
01
Table 19-10. TRANGE Trace Range Encoding
1, 2
Table
1
Trace only in address range from comparator C to 0x7FFFFF
Table 19-8. DBGTCR Field Descriptions
Trace only in address range from 0x0000 to comparator D
Section 19.4.5.2, “Trace Modes“
MC9S12XDP512 Data Sheet, Rev. 2.21
19-12.
0
5
TRANGE
Trace from all addresses (No filter)
0
4
Tracing Source
Description
Both CPU and XGATE
No tracing requested
Tracing Source
XGATE
for detailed trace mode descriptions. In normal
0
3
CPU
TRCMOD
Chapter 19 S12X Debug (S12XDBGV2) Module
Table
0
2
19-9.
Table
19-10.
0
1
TALIGN
0
0
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