MC9S12XDT512MAA Freescale, MC9S12XDT512MAA Datasheet - Page 704
MC9S12XDT512MAA
Manufacturer Part Number
MC9S12XDT512MAA
Description
Manufacturer
Freescale
Datasheet
1.MC9S12XDT512MAA.pdf
(1348 pages)
Specifications of MC9S12XDT512MAA
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
32KB
# I/os (max)
59
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XDT512MAA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 19 S12X Debug (S12XDBGV2) Module
19.3.1.9
Read: Anytime
Write: Anytime when DBG not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the
targeted next state while in State2. The matches refer to the match channels of the comparator match
control logic as depicted in
Register
associated DBGXCTL control register.
706
SC[3:0]
0x0027
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Reset
W
R
(DBGXCTL)”. Comparators must be enabled by setting the comparator enable bit in the
Debug State Control Register 2 (DBGSCR2)
0
0
7
Match3 triggers to State3....... Match1 triggers to final state....... Other matches have no effect
Match1 triggers to State3....... Match0 triggers final state....... Other matches have no effect
Match2 triggers to State3....... Match0 triggers final state....... Other matches have no effect
Match0 triggers to State2....... Match1 triggers to State3....... Other matches have no effect
Match0 triggers to State2....... Match2 triggers to State3....... Other matches have no effect
Match1 triggers to State2....... Match3 triggers to State3....... Other matches have no effect
Unimplemented or Reserved
Figure 19-11. Debug State Control Register 2 (DBGSCR2)
0
0
6
Figure 19-1
Table 19-21. State1 Sequencer Next Sate Selection
Match2 triggers to final state....... Other matches have no effect
Match2 triggers to State2....... Other matches have no effect
Match2 triggers to State3....... Other matches have no effect
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
and described in
Any match triggers to final state
Any match triggers to state2
Any match triggers to state3
0
0
4
Description
Reserved
Reserved
Reserved
Reserved
Section 19.3.1.11.1, “Debug Comparator Control
SC3
0
3
SC2
0
2
Freescale Semiconductor
SC1
0
1
SC0
0
0
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