A80960HD80S L2GK Intel, A80960HD80S L2GK Datasheet - Page 18

A80960HD80S L2GK

Manufacturer Part Number
A80960HD80S L2GK
Description
Manufacturer
Intel
Datasheet

Specifications of A80960HD80S L2GK

Family Name
i960
Device Core Size
32b
Frequency (max)
80MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Supply Voltage (max)
3.45V
Operating Supply Voltage (min)
3.15V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
168
Package Type
CPGA
Lead Free Status / RoHS Status
Compliant
80960HA/HD/HT
18
Table 7.
80960Hx Processor Family Pin Descriptions (Sheet 3 of 4)
BSTALL
XINT7:0
HOLDA
HOLD
BREQ
CT3:0
Name
BOFF
NMI
Type
R(Q)
H(Q)
B(Q)
H(Q)
B(Q)
H(Z)
R(Z)
A(E)
A(E)
S(L)
H(1)
B(0)
S(L)
R(0)
R(0)
B(Z)
A(L)
O
O
O
O
I
I
I
I
HOLD REQUEST signals that an external agent requests access to the
processor’s address, data, and control buses. When HOLD is asserted, the
processor:
Completes the current bus request.
Asserts HOLDA and floats the address, data, and control buses.
When HOLD is deasserted, the HOLDA pin is deasserted and the processor
reassumes control of the address, data, and control pins.
HOLD ACKNOWLEDGE indicates to an external master that the processor has
relinquished control of the bus. The processor grants HOLD requests and enters
the HOLDA state while the RESET pin is asserted.
HOLDA is never granted while LOCK is asserted.
BUS BACKOFF forces the processor to immediately relinquish control of the bus
on the next clock cycle. When READY/BTERM is enabled and:
When BOFF is asserted, the address, data, and control buses are floated on the
next clock cycle and the current access is aborted.
When BOFF is deasserted, the processor resumes by regenerating the aborted
bus access.
See
BUS REQUEST indicates that a bus request is pending in the bus controller.
BREQ does not indicate whether or not the processor is stalled. See BSTALL for
processor stall status. BREQ may be used with BSTALL to indicate to an external
bus arbiter the processor’s bus ownership requirements.
BUS STALL indicates that the processor has stalled pending the result of a
request in the bus controller. When BSTALL is asserted, the processor must
regain bus ownership to continue processing (i.e., it may no longer execute
strictly out of on-chip cache memory).
CYCLE TYPE indicates the type of bus cycle currently being started or processor
state. CT3:0 encoding follows:
EXTERNAL INTERRUPT pins are used to request interrupt service. These pins
may be configured in three modes:
Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated
inputs may be programmed to be level (low or high) or edge (rising or falling)
sensitive.
Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt
pins are level sensitive in this mode.
Mixed Mode: The XINT7:5 pins act as dedicated sources and the XINT4:0 pins
act as the five most significant bits of a vectored source. The least significant bits
of the vectored source are set to “010” internally.
NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.
NMI is the highest priority interrupt source. NMI is falling edge triggered.
Cycle Type
Program-initiated access using 8-bit bus
Program-initiated access using 16-bit bus
Program-initiated access using 32-bit bus
Event-initiated access using 8-bit bus
Event-initiated access using 16-bit bus
Event-initiated access using 32-bit bus
Reserved
Reserved for future products
Reserved
Figure 16 on page 48
for BOFF timing requirements.
Description
ADSCT3:0
00000
00001
00010
00100
00101
00110
00X11
01XXX
1XXXX
Datasheet

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