A80960HD80S L2GK Intel, A80960HD80S L2GK Datasheet - Page 6
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A80960HD80S L2GK
Manufacturer Part Number
A80960HD80S L2GK
Description
Manufacturer
Intel
Datasheet
1.A80960HD80S_L2GK.pdf
(104 pages)
Specifications of A80960HD80S L2GK
Family Name
i960
Device Core Size
32b
Frequency (max)
80MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Supply Voltage (max)
3.45V
Operating Supply Voltage (min)
3.15V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
168
Package Type
CPGA
Lead Free Status / RoHS Status
Compliant
Contents
Revision History
6
September 2002
July 1998
August 2004
Date
Revision
008
007
009
To address the fact that many of the package prefix variables have
changed, all package prefix variables in this document are now indicated
with an "x".
Formatted the datasheet in a new template.
In
In
In
In
In
In
Down)” on page
In
In
In
In
In
In
• Removed operating frequency of 16/32 (bus/core) from 80960HD.
• Removed operating frequency of 20/60 (bus/core) from 80960HT.
• Removed core speed of 32 MHz and bus speed of 16 MHz, and order
• Removed core speed of 60 MHz and bus speed of 20 MHz, and order
• Removed core speed of 32 MHz and bus speed of 16 MHz, and order
• Removed core speed of 60 MHz and bus speed of 20 MHz, and order
• Revised 1.2 Gbyte Internal Bandwidth (75 MHz) to 1.28 Gbyte Internal
• Added paragraph two and
• Corrected minor typeset and spacing errors.
• BREQ; Revised description.
• ONCE; last sentence, changed ‘low’ to ‘high’.
• TDI and TMS; removed last sentence stating, “Pull this pin low when
• Added insert package marking diagram.
• Added insert package marking diagram.
• Corrected TDO (‘O’ was zero) and revised alphabetical ordering.
• Corrected TDO (‘O’ was zero) and revised alphabetical ordering.
• Revised V
• Added section.
• Added footnote (1) to I
• Added footnote (10) to C
“32-Bit Parallel Architecture” on page
Table 5 “80960HA/HD/HT Package Types and Speeds” on page
“32-Bit Parallel Architecture” on page
Section 3.0, “Package Information” on page
Table 7 “80960Hx Processor Family Pin Descriptions” on page
Figure 2 “80960Hx 168-Pin PGA Pinout—View from Top (Pins Facing
Figure 4 “80960Hx 208-Pin PQ4 Pinout” on page
Table 10 “80960Hx PQ4 Pinout—Signal Name Order” on page
Table 11 “80960Hx PQ4 Pinout—Pin Number Order” on page
Section 4.1, “Absolute Maximum Ratings” on page
Section 4.5, “VCCPLL Pin Requirements” on page
Table 22 “80960Hx DC Characteristics” on page
number A80960HD32-S-L2GG from the 168L PGA package, 80960HD
device.
number A80960HT60 from the 168L PGA package, 80960HT device.
number FC80960HD32-S-L2GL from the 208L PQFP package,
80960HD device.
number FC80960HT60-S-L2G2 from the 208L PQFP package,
80960HT device.
Bandwidth (80 MHz).
and Speeds” on page
not in use.”
CC
20:
to VCC5 for Voltage on Other Pins with respect to V
14.
LO
IN
notes column for TDO pin.
Table 5 “80960HA/HD/HT Package Types
, C
OUT
History
and C
1:
1:
I/O
14:
pin.
40:
26:
39:
37:
Datasheet
29:
16:
27:
14:
SS
.