KC80526LY400128 Intel, KC80526LY400128 Datasheet - Page 11

• Manufacturer Part Number: KC80526LY400128
• Manufacturer: Intel

Specifications of KC80526LY400128

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.1.4
Table 4 lists the processor and PIIX4E/M sideband interface
signals. The voltage level for these signals is determined by
V_CPUIO.
FERR#
CPURST
IGNNE#
INIT#
INTR
NMI
A20M#
SMI#
STPCLK#
Name
Processor and PIIX4E/M Sideband (9
Signals)
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Type
N/C
ID
ID
ID
ID
ID
ID
ID
O
V_CPUIO
V_CPUIO
V_CPUIO
V_CPUIO
V_CPUIO
V_CPUIO
V_CPUIO
V_CPUIO
V_CPUIO
Voltage
Table 4. Processor/PIIX4E/M Sideband Signal Descriptions
Description
Numeric Coprocessor Error: This pin functions as a FERR# signal supporting
coprocessor errors. This signal is tied to the coprocessor error signal on the processor
and is driven by the processor to the PIIX4E/M.
Processor Reset: The signal is not used in the Celeron processor mobile module
MMC-1.
Ignore Error: This open-drain signal is connected to the Ignore Error pin on the
processor and is driven by the PIIX4E/M.
Initialization: INIT# is asserted by the PIIX4E/M to the processor for system
initialization. This signal is an open-drain.
Processor Interrupt: INTR is driven by the PIIX4E/M to signal the processor that an
interrupt request is pending and needs to be serviced. This signal is an open-drain.
Non-Maskable Interrupt: NMI is used to force a non-maskable interrupt to the
processor. The PIIX4E/M ISA bridge generates NMI when either SERR# or IOCHK# is
asserted, depending on how the NMI Status and Control Register is programmed. This
signal is an open-drain.
Address Bit 20 Mask: When enabled, this open-drain signal causes the processor to
emulate the address wraparound at 1 MB, which occurs on the Intel 8086 processor.
System Management Interrupt: SMI# is an active low synchronous output from the
PIIX4E/M that is asserted in response to one of many enabled hardware or software
events. The SMI# open-drain signal can be an asynchronous input to the processor.
However, in this chip set SMI# is synchronous to PCLK.
Stop Clock : STPCLK# is an active low synchronous open-drain output from the
PIIX4E/M that is asserted in response to one of many hardware or software events.
STPCLK# connects directly to the processor and is synchronous to PCICLK. When the
processor samples STPCLK# asserted, it responds by entering a low power state (Quick
Start). The processor will only exit this mode when this signal is deasserted.
Intel Celeron
At 400 MHz, 366 MHz, 333 MHz, and 300 MHz
Processor Mobile Module MMC-1
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