KC80526LY400128 Intel, KC80526LY400128 Datasheet - Page 19

• Manufacturer Part Number: KC80526LY400128
• Manufacturer: Intel

Specifications of KC80526LY400128

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Table 11 summarizes the key specifications for the MMC-1 connector.
4.0
4.1
The Celeron processor mobile module MMC-1 is offered at
speeds of 400 megahertz, 366 megahertz, 333 megahertz,
300 megahertz, and 266 megahertz. All processor speeds
have a PSB speed of 66 megahertz.
4.2
The on-die L2 cache is 128 kilobytes, is four-way set
associative, and runs at the speed of the processor core.
4.3
Intel’s 82443DX Host Bridge system controller combines the
mobile Celeron processor bus controller, the DRAM
controller, and the PCI bus controller into one component.
The 82443DX Host Bridge has multiple power management
features designed specifically for notebook systems such as:
CLKRUN#, a feature that enables controlling of the PCI
System Management RAM (SMRAM) power
clock on or off.
The 82443DX Host Bridge suspend modes, which
include Suspend-to-RAM (STR), Suspend-to-Disk
(STD), and Powered-on-Suspend (POS).
management modes, which include Compatible
SMRAM (C_SMRAM) and Extended SMRAM
(E_SMRAM). C_SMRAM is the traditional SMRAM
feature implemented in all Intel PCI chipsets.
E_SMRAM is a new feature that supports write-back
cacheable SMRAM space up to 1 megabyte. To
minimize power consumption while the system is idle,
FUNCTIONAL DESCRIPTION
Celeron Processor Mobile Module MMC-1
L2 Cache
The 82443DX Host Bridge System
Controller
Parameter
Material
Electrical
Mechanical
Contact
Housing
Current
Voltage
Insulation Resistance
Termination Resistance
Capacitance
Mating Cycles
Connector Mating Force
Contact Unmating Force
Condition
Table 11. Connector Specifications
Copper Alloy
Thermo Plastic Molded Compound: LCP
0.5 A
50 VAC
100 M minimum at 200 VDC
50 m maximum
5 pF maximum per contact
50 cycles
3.2 oz per contact
0.35 oz per contact
4.3.1
The MMC-1 connector signaling interface supports the
82443DX Host Bridge standard mode, memory
configurations, and modes of operation. This allows the
memory interface to support the following:
Memory features not supported by the 82443DX Host Bridge
system controller standard MMC-1 mode are:
The 82443DX Host Bridge system controller supports DRAM
technologies EDO and SDRAM. These memory types should
not be mixed in the system, so that all DRAM in all rows
(RAS[5:0]#) must be of the same technology. The 82443DX
Host Bridge system controller targets 60-nanosecond EDO
DRAMs, and 66-megahertz SDRAMs.
The Celeron processor mobile module’s clocking
architecture supports the use of SDRAM. Tight timing
requirements of the 66-megahertz SDRAM clocks allow all
host and SDRAM clocks to be generated from the same
clocking architecture on the system electronics. For
complete details about using SDRAM memory and for trace
Intel Celeron
One set of memory control signals, sufficient to support
One CKE signal for each bank.
Support for eight banks of memory.
Second set of memory address lines (MAA[13:0]).
Accelerated Graphics Port (AGP).
the internal 82443DX Host Bridge clock is turned off
(gated off). This is accomplished by setting the G_CLK
enable bit in the power management register in the
82443DX through the system BIOS.
up to three SO-DIMM sockets and six banks of SDRAM
at 66 megahertz.
At 400 MHz, 366 MHz, 333 MHz, and 300 MHz
Specification
Memory Organization
Processor Mobile Module MMC-1
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