KC80526LY400128 Intel, KC80526LY400128 Datasheet - Page 9

• Manufacturer Part Number: KC80526LY400128
• Manufacturer: Intel

Specifications of KC80526LY400128

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.1.2
Table 2 lists the memory interface signals.
MECC[7:0]
RASA[5:0]# or
CSA[5:0]#
CASA[7:0]# or
DQMA[7:0]
MAB[9:0]#
MAB[10]
MAB[12:11]#
MAB[13]
MWE[A, B]#
SRAS[A, B]#
SCAS[A, B]#
CKE[A, B]
MD[63:0]
Name
Memory (108 Signals)
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Type
I/O
I/O
O
O
O
O
O
O
O
Voltage
V_3
V_3
V_3
V_3
V_3
V_3
V_3
V_3
V_3
Memory ECC Data: These signals carry Memory ECC data during access to DRAM.
ECC is not supported on the Celeron processor mobile module.
Row Address Strobe (EDO): These pins select the DRAM row.
Chip Select (SDRAM): These pins activate the SDRAMs. SDRAM accepts any
command when its CS# pin is active low.
Column Address Strobe (EDO): These pins select the DRAM column.
Input/Output Data Mask (SDRAM): These pins act as synchronized output enables
during a read cycle and as a byte mask during a write cycle.
Memory Address (EDO/SDRAM): This is the row and column address for DRAM. The
82443DX Host Bridge system controller has two identical sets of address lines (MAA
and MAB#). The Celeron processor mobile module MMC-1 supports only the MAB set of
address lines. For additional addressing features, please refer to the Intel
PCIset Datasheet.
Memory Write Enable (EDO/SDRAM): MWEA# should be used as the write enable for
the memory data bus.
SDRAM Row Address Strobe (SDRAM): When active low, this signal latches Row
Address on the positive edge of the clock. This signal also allows Row access and pre-
charge.
SDRAM Column Address Strobe (SDRAM): When active low, this signal latches
Column Address on the positive edge of the clock. This signal also allows Column
access.
SDRAM Clock Enable (SDRAM): When these signals are deasserted, SDRAM enters
power-down mode. CKEB is NC and not used by the system electronics.
Memory Data: These signals are connected to the DRAM data bus. They are not
terminated on the Celeron processor mobile module MMC-1.
Table 2. Memory Signal Descriptions
Intel Celeron
At 400 MHz, 366 MHz, 333 MHz, and 300 MHz
Description
Processor Mobile Module MMC-1
440DX
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