MC9S12DP512CPVE Freescale, MC9S12DP512CPVE Datasheet - Page 114
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MC9S12DP512CPVE
Manufacturer Part Number
MC9S12DP512CPVE
Description
Manufacturer
Freescale
Datasheet
1.MC9S12DP512CPVE.pdf
(124 pages)
Specifications of MC9S12DP512CPVE
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
25MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
14KB
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.25V
Operating Supply Voltage (min)
2.35/4.5V
On-chip Adc
2(8-chx10-bit)
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
112
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
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Company
Part Number
Manufacturer
Quantity
Price
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FREESCAL
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Part Number:
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Company:
Part Number:
MC9S12DP512CPVER
Manufacturer:
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Quantity:
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MC9S12DP512 Device Guide V01.25
In Table A-19 the timing characteristics for master mode are listed.
Num
(CPOL 0)
(CPOL 1)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
10
11
12
13
1
1
2
3
4
5
6
9
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
(INPUT)
MISO
MOSI
SCK
SCK
SS
SCK Frequency
SCK Period
Enable Lead Time
Enable Lag Time
Clock (SCK) High or Low Time
Data Setup Time (Inputs)
Data Hold Time (Inputs)
Data Valid after SCK Edge
Data Valid after SS fall (CPHA=0)
Data Hold Time (Outputs)
Rise and Fall Time Inputs
Rise and Fall Time Outputs
1
PORT DATA
9
Characteristic
Table A-19 SPI Master Mode Timing Characteristics
2
MASTER MSB OUT
4
5
MSB IN
Figure A-7 SPI Master Timing (CPHA=1)
1
2
6
4
2
12
12
11
BIT 6 . . . 1
BIT 6 . . . 1
Symbol
t
t
t
f
t
wsck
t
t
lead
vsck
t
t
t
t
sck
sck
t
vss
lag
su
ho
rfo
hi
rfi
1/2048
Min
20
—
—
—
—
—
—
—
2
8
8
13
13
MASTER LSB OUT
LSB IN
Typ
1/2
1/2
1/2
—
—
—
—
—
—
—
—
—
3
Max
2048
1 2
30
15
—
—
—
—
—
—
8
8
PORT DATA
Unit
f
t
t
t
t
bus
bus
ns
ns
ns
ns
ns
ns
ns
sck
sck
sck