MC9S12DP512CPVE Freescale, MC9S12DP512CPVE Datasheet - Page 57
![no-image](/images/manufacturer_photos/0/2/261/freescale_sml.jpg)
MC9S12DP512CPVE
Manufacturer Part Number
MC9S12DP512CPVE
Description
Manufacturer
Freescale
Datasheet
1.MC9S12DP512CPVE.pdf
(124 pages)
Specifications of MC9S12DP512CPVE
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
25MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
14KB
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.25V
Operating Supply Voltage (min)
2.35/4.5V
On-chip Adc
2(8-chx10-bit)
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
112
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12DP512CPVE
Manufacturer:
JAE
Quantity:
1 000
Company:
Part Number:
MC9S12DP512CPVE
Manufacturer:
FREESCAL
Quantity:
316
Company:
Part Number:
MC9S12DP512CPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12DP512CPVE
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MC9S12DP512CPVER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC
signal, when enabled, is used to indicate that the current bus cycle is an unused or “free” cycle. This signal
will assert when the CPU is not using the bus.
The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts
(low power) oscillator is used or whether Pierce oscillator/external clock circuitry is used. The state of this
pin is latched at the rising edge of RESET. If the input is a logic low the EXTAL pin is configured for an
external clock drive or a Pierce Oscillator. If input is a logic high a Colpitts oscillator circuit is configured
on EXTAL and XTAL. Since this pin is an input with a pull-up device during reset, if the pin is left
floating, the default configuration is a Colpitts oscillator circuit on EXTAL and XTAL.
* Due to the nature of a translated ground Colpitts oscillator a
Figure 2-3 Colpitts Oscillator Connections (PE7=1)
DC voltage bias is applied to the crystal
Please contact the crystal manufacturer for crystal DC
bias conditions and recommended capacitor value C
MCU
EXTAL
XTAL
C
DC
*
C
1
C
2
DC
.
VSSPLL
MC9S12DP512 Device Guide V01.25
ceramic resonator
Crystal or
57