MC9S12DP512CPVE Freescale, MC9S12DP512CPVE Datasheet - Page 88
![no-image](/images/manufacturer_photos/0/2/261/freescale_sml.jpg)
MC9S12DP512CPVE
Manufacturer Part Number
MC9S12DP512CPVE
Description
Manufacturer
Freescale
Datasheet
1.MC9S12DP512CPVE.pdf
(124 pages)
Specifications of MC9S12DP512CPVE
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
25MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
14KB
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.25V
Operating Supply Voltage (min)
2.35/4.5V
On-chip Adc
2(8-chx10-bit)
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
112
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12DP512CPVE
Manufacturer:
JAE
Quantity:
1 000
Company:
Part Number:
MC9S12DP512CPVE
Manufacturer:
FREESCAL
Quantity:
316
Company:
Part Number:
MC9S12DP512CPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12DP512CPVE
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MC9S12DP512CPVER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
MC9S12DP512 Device Guide V01.25
A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Num C
2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.
3. All digital I/O pins are internally clamped to V
4. Those pins are internally clamped to V
5. This pin is clamped low to V
1
2
3
4
5
Human Body
Machine
Latch-up
The absolute maximum ratings apply when the device is powered from an external source.
Model
C Human Body Model (HBM)
C Machine Model (MM)
C Charge Device Model (CDM)
C
C
Latch-up Current at T
positive
negative
Latch-up Current at T
positive
negative
Table A-3 ESD and Latch-up Protection Characteristics
Series Resistance
Storage Capacitance
Number of Pulse per pin
positive
negative
Series Resistance
Storage Capacitance
Number of Pulse per pin
positive
negative
Minimum input voltage limit
Maximum input voltage limit
Table A-2 ESD and Latch-up Test Conditions
SSX
A
A
Rating
= 125 C
= 27 C
, but not clamped high. This pin must be tied low in applications.
Description
SSPLL
and V
SSX
and V
DDPLL
DDX
.
, V
SSR
Symbol
V
V
V
I
I
HBM
CDM
LAT
LAT
and V
MM
DDR
Symbol
R1
R1
or V
C
C
-
-
2000
+100
+200
Min
-100
-200
200
500
SSA
and V
Value
1500
100
200
-2.5
7.5
3
3
0
3
3
-
-
DDA
Max
-
-
-
-
-
.
Unit
Ohm
Ohm
pF
pF
V
V
Unit
mA
mA
V
V
V