MC9S12DP512CPVE Freescale, MC9S12DP512CPVE Datasheet - Page 70
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MC9S12DP512CPVE
Manufacturer Part Number
MC9S12DP512CPVE
Description
Manufacturer
Freescale
Datasheet
1.MC9S12DP512CPVE.pdf
(124 pages)
Specifications of MC9S12DP512CPVE
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
25MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
14KB
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.25V
Operating Supply Voltage (min)
2.35/4.5V
On-chip Adc
2(8-chx10-bit)
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
112
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
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MC9S12DP512 Device Guide V01.25
4.3 Security
The device will make available a security feature preventing the unauthorized read and write of the
memory contents. This feature allows:
The user must be reminded that part of the security must lie with the user’s code. An extreme example
would be user’s code that dumps the contents of the internal program. This code would defeat the purpose
of security. At the same time the user may also wish to put a back door in the user’s program. An example
of this is the user downloads a key through the SCI which allows access to a programming routine that
updates parameters stored in EEPROM.
4.3.1 Securing the Microcontroller
Once the user has programmed the FLASH and EEPROM (if desired), the part can be secured by
programming the security bits located in the FLASH module. These non-volatile bits will keep the part
secured through resetting the part and through powering down the part.
The security byte resides in a portion of the Flash array.
Check the Flash Block Guide for more details on the security configuration.
4.3.2 Operation of the Secured Microcontroller
4.3.2.1 Normal Single Chip Mode
This will be the most common usage of the secured part. Everything will appear the same as if the part was
not secured with the exception of BDM operation. The BDM operation will be blocked.
•
•
•
•
Protection of the contents of FLASH,
Protection of the contents of EEPROM,
Operation in single-chip mode,
Operation from external memory with internal FLASH and EEPROM disabled.
PE7 = XCLKS
VREGEN
Table 4-2 Clock Selection Based on PE7
1
0
Table 4-3 Voltage Regulator VREGEN
1
0
Internal Voltage Regulator enabled
Internal Voltage Regulator disabled, VDD1,2 and
VDDPLL must be supplied externally with 2.5V
Colpitts Oscillator selected
Pierce Oscillator/external clock selected
Description
Description