SC2200UFH-300 AMD (ADVANCED MICRO DEVICES), SC2200UFH-300 Datasheet - Page 106

• Manufacturer Part Number: SC2200UFH-300
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC2200UFH-300

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

External Elements
Choose C
111) to match the crystal’s load capacitance. The load
capacitance C
series with C
of the circuit. The parasitic capacitance is caused by the
chip package, board layout and socket (if any), and can
vary from 0 to 10 pF. The rule of thumb in choosing these
capacitors is:
Example:
Oscillator Startup
The oscillator starts to generate 32.768 KHz pulses to the
RTC after about 100 msec from when V
V
oscillation amplitude on the X32O pin stabilizes to its final
value (approximately 0.4V peak-to-peak around 0.7V DC)
in about 1 s.
C
achieve a high time accuracy, use crystal and capacitors
with low tolerance and temperature coefficients.
5.5.2.2
32.768 KHz can be applied from an external clock source,
as shown in Figure 5-6.
Connections
Connect the clock to the X32I ball, leaving the oscillator
output, X32O, unconnected.
Signal Parameters
The signal levels should conform to the voltage level
requirements for X32I, of square or sine wave of 0.0V to
V
approximately 50%. It should be sourced from a battery-
backed source in order to oscillate during power-down.
This assures that the RTC delivers updated time/calendar
information.
5.5.2.3
The timing generation function divides the 32.768 KHz
clock by 2
input for the seconds counter. This is performed by a
divider chain composed of 15 divide-by-two latches, as
shown in Figure 5-7.
Bits [6:4] (DV[2:0]) of the CRA Register control the follow-
ing functions:
• Normal operation of the divider chain (counting).
• Divider chain reset to 0.
• Oscillator activity when only V
112
BATMIN
CORE
1
(backup state).
can be trimmed to achieve precisely 32.768 KHz. To
C
Crystal C
C
L
1
amplitude. The signal should have a duty cycle of
= (C
= 3.6 pF, C
(2.4V) or V
External Oscillator
Timing Generation
15
1
1
and C
2
to derive a 1 Hz signal, which serves as the
* C
L
L
and in parallel with the parasitic capacitance
= 10 pF, C
“seen” by crystal Y is comprised of C
2
) / (C
2
2
= 3.6 pF
SB
capacitors (see Figure 5-5 on page
1
32580B
is higher than V
+ C
PARASITIC
2
) + C
BAT
PARASITIC
= 8.2 pF
power is present
SBMIN
BAT
is higher than
(3.0V). The
1
in
Battery
B
The divider chain can be activated by setting normal opera-
tional mode (bits [6:4] of CRA = 01x or 100). The first
update occurs 500 msec after divider chain activation.
Bits [3:0] of CRA select one the of fifteen taps from the
divider chain to be used as a periodic interrupt. The peri-
odic flag becomes active after half of the programmed
period has elapsed, following divider chain activation.
See Table 5-20 on page 117 for more details.
1
X32I
Figure 5-6. External Oscillator Connections
V
BAT
C
C
Figure 5-7. Divider Chain Control
32.768 KHz
F
F
1
2
AMD Geode™ SC2200 Processor Data Book
POWER
2
X32O
2
CLKIN
CRA Register
(X32I)
Divider Chain
DV2 DV1 DV0
R
R
3
6
2
1
2
Clock Generator
5
To other
modules
Reset
32.768 KHz
4
OUT
13
NC
2
3.3V square wave
X32O
14
2
15
SuperI/O Module
To other
2
modules
R
R
C
External
1
2
F
Internal
Enable
1 Hz
Oscillator
= 30 KΩ
= 30 KΩ
= 0.1 μF